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ml505_mig_design
Xilinx开发板ML505的DDRII示例程序,使用Verilog,调用MIG,编译环境ISE11.1(Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1)
- 2010-05-13 02:39:04下载
- 积分:1
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HUAWEI_FPGA
华为内部资料,华为FPGA全套资料,包括华为的专利设计(Internal information Huawei Huawei FPGA complete information, including Huawei' s patented design)
- 2020-12-21 18:19:08下载
- 积分:1
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LED-clock-display
利用单片机控制LED时钟显示,以及闹钟,程序较大,但比较简单易懂。(LED clock display)
- 2013-03-10 10:15:37下载
- 积分:1
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I2C
I2C verilog源代码实例并带有验证平台(iic source code and testbench)
- 2018-06-08 15:46:23下载
- 积分:1
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PipelineSim
一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。(A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of parallel division, 16-bit word length, fixed-length instructions, Verilog source code, top level design. Simple structure, conflict resolution is also very simple, a small amount of code.)
- 2012-06-24 22:19:14下载
- 积分:1
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信道编码的差分源代码
主要用于信道编码,可以防止相位的翻转,计算码元之间的相位变化以后,做差分传输,接收端根据前一码元的相位进行解差分。
- 2022-01-30 16:51:06下载
- 积分:1
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acx735_usb_ddr3_tft
说明: USB传图至fpga板缓存至DDR内,FPGA再读出图像数据,显示在TFT彩屏上;(USB to the FPGA board cache DDR, FPGA read out the image data, display on the TFT color screen;)
- 2021-01-30 18:06:45下载
- 积分:1
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FPGA-design-of-wavelet-filter
基于Verilog的小波滤波器程序设计的总结文档。(Verilog based wavelet filter program design summary document.)
- 2016-03-09 11:19:24下载
- 积分:1
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verilog rgb_yuv
AD8176的控制verilog编写,可实现RGB的自由切换,16通道进,9通道输出。
- 2022-01-22 16:34:08下载
- 积分:1
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dct01
Verilog编写的串口通讯下解码状态机(Verilog serial communication prepared under the decoder state machine)
- 2011-01-17 02:40:41下载
- 积分:1