verilog rgb_yuv

基于VHDL编写的10进制显示输出，基于16进制的10进制控制，适合初学者(VHDL-based display output written in decimal, hexadecimal, 10 hexadecimal-based control, suitable for beginners)

pcf8563，在quartusII下VERILOG编写的数字时钟程序，8位数码管显示(pcf8563, written in quartusII VERILOG digital clock program, eight digital display)

如何编写测试文件，，test bench的编写方法和是列，，总结的非常好的东西(how to code test bench in verilog)

The IEEE 30-bus modified test system has 6 synchronous machines with IEEE type-1 exciters, 4 of which are synchronous compensators, 36 buses, 37 transmission lines, 10 transformers and 21 constant impedance loads. The total load demand is 283.4 MW and 126.2 MVAr.

使用VHDL编写语言，巧妙的利用计数器和循环输出一个坐标系，由于VHDL出现负数比较麻烦，全部由正数代替，输出一个原点在中心，半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。(Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive number, the output an origin at the center, radius 128 256 256 coordinates. Convenient coordinate transformation and coordinate to do with this algorithm.)

CFI控制器顶层模块，32位wishbone总线经典接口，用于简化对CFI flash(如块)的访问解锁、删除和编程。(Top level of CFI controller with 32-bit Wishbone classic interface)

说明：  鉴于stm32在keil平台上的ADC采集转化，在LCD屏上显示程序(voltage acquisition adc)

说明：  串口通信vivado实现，带有仿真文件，可实现数据收发(the uart program based on vivado)

黑金开发板对时钟信号的编写实验以及调试，相关代码如压缩包所示(CLOCK FPGA)

这段代码在 verilog 的用于计算 2 的浮点数，需要计算的保险带的 all32 位，它可以用。