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ControlUnit
Control Unit VHDL code. Xilinx Spartan 3E board
- 2012-03-15 13:29:40下载
- 积分:1
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Norflash
用verilog hdl写的Norflash控制器,可实现单字节读写,扇区擦除。(Norflash controller edit by Verilog hdl,it can read or write by Byte,or erase the sector.)
- 2021-03-29 16:29:11下载
- 积分:1
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bianyuanjiance
图像采集 VGA输出 图像的边缘 ov7670(V image acquisition VGA output image edge)
- 2020-06-21 13:20:06下载
- 积分:1
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GFP
这是一个EOS项目中的GFP成帧结构,能够容错,可以配置字节域(This is an EOS project GFP Framing structure, be able to fault-tolerant, can be configured byte domain)
- 2009-03-26 10:58:49下载
- 积分:1
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quartus2tutorial
说明: 自己收集的quartus2 教程以及vhdl语言教程,和如何在quartus中使用modism仿真 ,希望对大家有用(Tutorial quartus2 own collection, as well as language tutorials vhdl and quartus how to use modism, useful for all of us hope)
- 2009-07-27 09:09:22下载
- 积分:1
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This procedure for the Verilog control ADC all procedures can be applied to test
此程序为Verilog控制ADC的全部程序,已检验可以应用-This procedure for the Verilog control ADC all procedures can be applied to test
- 2023-04-20 20:25:03下载
- 积分:1
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ISP的IP核,下载即可用,解压到指定目录下就可以了,参照里面的read me....
ISP的IP核,下载即可用,解压到指定目录下就可以了,参照里面的read me.-ISP of the IP core, can be used to download, unzip to the specified directory can be a light inside the read me.
- 2022-02-02 17:09:38下载
- 积分:1
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用Verilog HDL语言编写的AT24C04程序,并用数码管显示,已经过测试,很好用...
用Verilog HDL语言编写的AT24C04程序,并用数码管显示,已经过测试,很好用-With the Verilog HDL language of the AT24C04 procedures and use digital tube display, has been tested, very good to use--
- 2022-03-19 15:00:00下载
- 积分:1
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leadingzero
使用并行结构对32位数据进行前导零检测,使用Verilog编程(Use parallel structure to the 32-bit data, leading zero detection, using Verilog Programming)
- 2010-05-12 10:48:36下载
- 积分:1
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04_uart_test
说明: 基于FPGA,用verilog hdl语言实现串口收发实验(Based on FPGA, using Verilog HDL language to achieve serial port transceiver experiment)
- 2021-03-14 13:43:49下载
- 积分:1