第七部分 串口Uart通信例程

verilog程序仿真滤波器 16阶 运用加法器和乘法器 40KHZ 16位并入并出

说明：  Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC

含异步清零和同步清零的计数器的设计，内容是源代码，以及相关文件，打开即可(Clear cleared asynchronous and synchronous with the counter design, content source code and related documents, can be opened)

CSS配合jquery制作完美漂亮的时钟，貌似在IE8下时钟不能获取时间啊！支持ie9、chrome、safari、firefox、opera （Chrome显示效果最佳，IE9下时钟无法工作）日历和骰子是原创，CSS3时钟并非原创但经过改良支持opera。数字日历的兼容性不错，圆形时钟就差点了，也希望一起交流，共同改进。(CSS with the jquery make perfect beautiful clock, seemingly in IE8 under the clock can not get the time ah! Support ie9, chrome, safari, firefox, opera (Chrome show the best results, the clock does not work under IE9) calendar and dice is original, CSS3 clock is not original but after improved support opera. Digital calendar compatibility is good, almost round the clock on, and also hope together, and work together to improve.)

VHDL由简单存储器，计数器等搭建最终实现8位的cpu设计(VHDL realization 8 of cpu design)

matlab科斯塔斯环的仿真，有波形，很实用的程序(matlab costas m programm)

说明：  用Verilog实现的基于FPGA的简单避障游戏(A game based on FPGA,using Verilog)

是codic算法实现atan的C程序，包括定点和浮点程序，已经通过验证。(Atan is codic algorithm of C procedures, including fixed-point and floating-point procedures, has been validated.)

多功能数字钟，在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)

在FPGA平台实现SPI传输协议开发，SPI为三总线式。(Implementation of SPI transmission protocol development on FPGA platform)