第七部分 串口Uart通信例程

SRAM 读写实验，SRAM存储器的读写操作，Verilog源码有助于提高代码coding能力。使用例程。(SRAM write and read)

说明：  用verilog HDL编程实现的基于DAC0832的三角波信号，可借鉴编程实现DAC0832芯片控制(Programming with verilog HDL DAC0832-based triangular wave signal, we may learn programming DAC0832 chip control)

40M时钟输入经过iserdes倍频到960M(input 40M o clock and output 960M )

8倍抽取的DDC模块。verilog写的，调试通过(failed to translate)

用blockram实现移位寄存器，开发语言为verilog hdl(Shift register with blockram achieve the development language for the verilog hdl)

verilog 串口多字节发送程序，波特率计算公式如下：cnt_baud =(1/9600bps)/(1/crystal_frq(Mhz))-1；可以发送多个字节的数据，但是字节数是固定的

VHDL编写加扰和解扰程序，程序连在一起仿真正确，并通过下板子抓数据验证程序没问题-Write scrambling and descrambling program, VHDL program together properly simulation, and data validation procedures is caught by the board no problem

初学cpu结构的很好的verilog代码的示例，适合初学者(novice cpu structure of the good verilog code examples for beginners)

用verilog写的卷积码的编码程序以及viterbi译码程序(Use verilog write convolution code coding procedures and viterbi decoding program)

说明：  假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 +　寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)