SPI 主核心

Blessing_3_v3_9_6稳定盈利set，仅限AUDNZD货币对，周期M1。 使用本压缩包内的SET，LAF默认是15，根据历史测试来看具有较大的风险，需要手动规避数据。 合理设置为LAF=8，请自行设置和调试，找到自己合适的风险值。 (Blessing_3_v3_9_6 stable profit set, only AUDNZD currency pairs, cycle M1. Use this package in the SET, the default is 15 fans, according to the angles of history test has great risk, need to avoid data manually. Reasonable set to fans = 8, please make your own setting and debugging, find their proper risk value.)

在以太网通信中，连接MAC与物理层需要使用MII接口，此程序提供了MII接口的详细设计。

周立功Fusion StartKit，fpga开发板的实验例程，Flash Memory初始化RAM实验(ZLG Fusion StartKit, fpga development board test routines Flash Memory Initialize RAM experiments)

DDR3控制器源码，针对XilinxFPGA的DDR3控制器的源码，已经验证通过。(DDR3 Controller，complete DDR3 controll，have pass verificaion.)

Decimation-In-Time Fast Fourier Transform I"ve tried to make the implementation simple and well documented. I have not tried to make it efficient. dit.v - Contains main module. buffer.v - Contains a module for a single butterfly step. generate_twiddlefactors.py - Contains function to generate a verilog file with twiddlefactors. twiddlefactors_N.v.t - Template used to generate verilog file. dut_dit.v - A wrapper around the "dit" module to allow verification with MyHDL. qa_dit.py - A MyHDL test bench for verification. Requires MyHDL, iverilog and numpy to be installed. pyfft.py - Generates output of intermediate FFT stages. Useful for debugging.

1024点fft verilog hdl(1024-point fft verilog hdl)

说明：  nios开发板电路图CycloneII_NiosII_2C35_Rev02_DB_SCH.zip(nios development board circuit CycloneII_NiosII_2C35_Rev02_DB_SCH.zip)

乘法器在FPGA中，使用的非常多，里面非常详细的介绍了乘法器的使用，源代码，仿真，MATLAB程序，

成功解决FPGA设计时序问题的三大点.word说明文档，很详细(FPGA design timing problems successfully solved the three points)

说明：  基于蜂鸟E203riscv系统的DMA外设代码(DMA code based on hbird_e203 system)