平行 CRC verilog 代码生成器

根据模块的时序图自己写出的触发与接收程序，有效范围4m，精度2mm，设计一个算法使模块能输出精确的时间，本模块采用50MHz时钟信号，若晶振不同，请将程序中计数器位数改掉。

这个是DE2上的SDRAM 四个端口的驱动代码，相当实用！(This is a four-port SDRAM on a DE2 driver code, very useful!)

51数字钟带各种扩展年，月，日等并且可预置。用汇编语言写的(51 digital clock with extended assembly language)

fpga实现ＣＡＮ总线控制器源码,每个项目都有说明文件，介绍使用方法。(fpga CAN Bus Controller source, each with explanatory documents on the use of methods.)

说明：  阿尔泰PCI8664的采集卡labview程序(PCI8664，labview，programm)

timblogiw.c timberdale FPGA LogiWin Video In driver.

实现SVPWM的算法实现和仿真，基于FPGA平台用VHDL语言编写(Realization and Simulation of algorithm for realizing SVPWM)

XILINX中LWIP协议例子应用指南，有实际例子(Examples of applications in LWIP agreement XILINX Guide, a practical example)

《CPLDFPGA嵌入式应用开发技术白金手册》源代码，涉及FPGA/CPLD的各个方面，键盘扫描，LED扫描等简单程序及滤波器等的设计(" CPLDFPGA platinum embedded application development technology handbook" source code, related to FPGA/CPLD all aspects of the keyboard scanning, LED scanning filters, such as simple procedures and design)

采用verilog语言基于查找表描述8b10b编码源代码(Using Verilog language to describe 8B10B encoding source code based on look-up table)