verilog三阶数字锁相环

SRAM读写测试，每秒进行一次单字节SRAM读写，使用chipscope观察时序波形(SRAM read and write test, a single byte SRAM read and write every second, using chipscope to observe the timing waveform)

说明：  VHDL实现的算术逻辑计算单元（ALU），包括modersim测试文件，即仿真结果。(VHDL implementation of the arithmetic logic calculation unit (ALU), including modersim test file, the simulation results.)

xilinx的zed板详细开发资料，对初学者和开发人员都有帮助(The Xilinx zed board detailed development information, helpful for beginners and developers)

Token Bucket Filter queue.

时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。 OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system. OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)

, verilog语言实现的高速DACAD9747的SPI接口及寄存器配置

自己编写的verilog语言 PWM实现的一种方法希望有用(verilog PWM)

说明：  异步VLSI大规模电路设计的圣经，一本很经典的异步电路入门书籍(The Bible of Asynchronous VLSI Large Scale Circuit Design, A Classic Introduction to Asynchronous Circuits)

完整的Verilog验证模型，包括设备完整的状态。(Complete verilog Verification Model)

用Verilog实现自动售货机功能，代码较初级。易懂，内含test文件。(Automatic vending machines function with Verilog code than the primary. Understandable, containing test files.)