使用DA FIR滤波器

设计了车载视频显示系统，设计了基于FPGA系统结构的车载视频显示电路板，利用FPGA显示视频控制，采集通道时许控制等。(The on-board video display system design, design the system structure based on FPGA video shows the circuit board, using the FPGA show video control, acquisition channel make control, etc )

利用verilog HDL逐点比较法实现直线和圆弧插补(Use verilog HDL by-point comparison method to achieve linear and circular interpolation)

说明：  sata3.0协议及FPGA各模块实现,有代码及文档说明。(Sata3.0 protocol and FPGA module implementation, with code and documentation.)

uart 发送模块接收模块及tb，其中可以选择不同波特率进行收发，代码带有详细注释。(UART sending module and receiving module)

xilinx verilog FPGA驱动AD9613 数据采集DEMO程序(Xilinx Verilog FPGA drives AD9613 data acquisition DEMO program.)

ad9230的配置程序，差分输入输出，verilog(ad9230 configuration program, verilog)

fpga key test 入门 xilinx 黑金的板子(fpga key test xilinx)

基于查找表的DDS的Verilog实现，分为相位累加器模块、ROM模块和顶层DDS模块(Verilog implementation of DDS based on lookup table)

The IEEE 30-bus modified test system has 6 synchronous machines with IEEE type-1 exciters, 4 of which are synchronous compensators, 36 buses, 37 transmission lines, 10 transformers and 21 constant impedance loads. The total load demand is 283.4 MW and 126.2 MVAr.

MVB架构流程图。MVB开发用，大连海天资料(MVB development, Dalian Haitian data)