使用DA FIR滤波器

VHDL由简单存储器，计数器等搭建最终实现8位的cpu设计(VHDL realization 8 of cpu design)

QPSK调制的载波频偏估计，是一个可以调用的函数。接收端进行了一系列的处理。经典的Fitz法(QPSK-carrier frequence offset estimation_ Fitz)

de2 70 开发板的演示程序，verilog语言编写，视频输入输出(de2 70 development board demo program, verilog language written, video input and output)

agilex fpga description

Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.

数字逻辑与系统的关于所有的器件74LS的介绍，功能表(Digital Logic and System devices 74LS on the introduction of all the menu)

32-bit shifter, shifter, 32-bit.Very goog as a study file.

说明：  nios开发板电路图CycloneII_NiosII_2C35_Rev02_DB_SCH.zip(nios development board circuit CycloneII_NiosII_2C35_Rev02_DB_SCH.zip)

说明：  半带滤波器，工作在采样率122.88Msps上(Half-band filter, working at the sampling rate of 122.88 Msps)

Verilog代码为Sigma-Delta ADC的实现。Verilog是包含testbench。NDIFF V。V的冬天。readmem V。V梳状滤波器。combfilter_tb V。combfilter_wrap.vhd