verilog按键检测

IRIG_B解码器，直接解码IRIG_B DC(IRIG_B decoder)

fifo是一种先进先出的缓存器，广泛运用在跨时钟域设计，数据缓存中，根据读写可以同步，也可以异步，是一种非常好用的缓存器。

Verilog实现FPGA的VGA塞瑟条纹显示代码，测试完全正确，可以成功的实现功能。

Xilinx Sysgen User Guide

VerilogHDL教程，很详细全面的Verilog教程，循序渐进，由浅入深，十分好的学习资料(VerilogHDL tutorial, very detailed and comprehensive Verilog tutorial, step by step, progressive approach, a very good learning materials)

通过LED闪烁控制器的代码，使用Vivado工具配置定义一个IP核，在用户工程中可随意添加这个IP核作为设计的一部分，如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at random in user engineering. It is as convenient to call and integrate as the IP kernel with Vivado.)

基于xilinx公司的SPARTAN6系列芯片的高速全双工串行收发器(high-speed transceiver based on spartan 6 of Xilinx PFGA)

verilog 编写的ldpc编码，含有两个文件(LDPC written by Verilog)

A design on a DE270 FPGA with the use of CCD: a camera DC2 and a TRDB LTM after reading from the SRAM.

LDPC encoding code in 1/2code rate for DVB-T2