PWM 计数器

一个vivado和matalab混合编程的信号发生器，注意要把vivado里面的核文件路径改一下(A signal generator with mixed programming of vivado and matalab, pay attention to changing the path of the core file in vivado)

veriog code for fodm.It includes transmitter and receiver. Transmitter part has serial in parallel out, decoder, interleaver, IFFT and finally to the transmitter block. Receiver part has the reverse order to transmitter.

AHB_Lite 通信协议的FPGA Verilog 设计(AHB_Lite communication protocol Verilog design in FPGA)

FIR带通、带阻滤波器设计，需要输入截止频率以及容许偏差。(FIR band pass and band stop filter design)

FPGA控制AG9226进行采样的代码,并用signaltap测试了一下其正确性(FPGA control AG9226 to sample the code, and use signaltap to test the correctness of the demo.)

本程序使用Verilog语言实现了SPI接口的设计，可以直接烧到FPGA实现与MCU的通信,自带有测试文件。(The program uses the Verilog language design SPI interface, you can burn directly communicate with the FPGA, MCU, comes with a test file.)

ds18b20温度传感器，通过状态机对传感器分别进行初始化，访问寄存器，读取数据，将读取到的数据显示到数码管当中，实现温度传感的功能。18b20主要是3个状态机，一个主状态机和两个嵌入的状态机。

AD7760模数转换，使能滤波器功能，简单易懂，可进行各种配置 全功能支持，并附加使用说明(AD7760 Full Function Support with Additional Instructions)

这是二十四进制计数器的源程序，有需要的同学可以参照一下！(This is 24 hexadecimal counter source, needy students can refer to you!)

使用verilog写的频率计，可切换档位(Frequency counter using verilog write switch stalls)