使用Verilog HDL的全加器的设计

这个源代码是EasyFPGA030的例程。欢迎大家下载、试用。谢谢大家的支持！

说明：  VIVADO HLS IMAGE 使用文档(vivado image processing example text of zynq)

非常好的verilog书 国际牛人写的 适合各个阶段学习的人(Very good Verilog books were written in the international cattle suitable for the various stages of learning)

应用背景关键技术Altera FPGA  ；CIII，Cyclone III implemented.16灰度320x240流视频信号发生器。

说明：  电路四倍频算法，具有去毛刺，整形功能，方向及计数(Circuit quadruple frequency algorithm, with deburring, shaping function)

基于quartus的布斯乘法器的verilog 实现。布斯乘法算法是计算机中一种利用数的2的补码形式来计算乘法的算法。该算法由安德鲁·唐纳德·布斯于1950 年发明，当时他在伦敦大学伯克贝克学院做晶体学研究。布斯曾使用过台式计算器，由于用这种计算器来做移位计算比加法快，他发明了该算法来加快计算速度。(The verilog codes of booth multiplier based on quartus. Booth multiplication algorithm is a computer algorithm using the complement form of number 2 to calculate the multiplication. The algorithm was invented in 1950 by Andrew Donald booth, who was working on crystallography at birkbeck college, university of London. Booth used a desktop calculator, and because it was faster to do shifts than to add, he invented the algorithm to speed up the calculations.)

说明：  在quartus下搭建的数字锁相环，能实现频率自动跟踪。(The digital phase-locked loop built under quartus can realize automatic frequency tracking.)

本控制器与博世参考模型测试

本程序是fpga控制flash的读写程序，包括了程序和仿真时的测试文件(fpga flash)

turbo码在LTE中的实现，并在fpga中得到了实现(turbo code in LTE implementations, and have been achieved in fpga)