任意基数分频VERILOG代码，经过了编译，可以修改数字改变分频。...

VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source

CH4CH2CH1VHDL 数字电路参考书所有程序5-CH4CH2CH1VHDL digital circuit reference all proceedings 5

endat 2.2 接口内核，发送命令至编码器或从编码器接收位置值(endat 2.2 interface cores, sending commands to the encoder or received the encoder position values)

verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.

VHDL语言实现H.264的opencore，内涵说明文档、源码和文献等资料。 -VHDL language H.264 realize the opencore, meaning that documents, information such as source code and documentation.

用VHDL语言编写的代码，以供大家学习和交流，方便大家学习！-prepared using VHDL code for all to study and exchange to facilitate learning!

一些verilo的经典实例，非常适合初学者(verilo of the classic examples, for beginners)

VHDL硬件描述语言与数字逻辑电路设计―― VHDL语言的基本知识和设计逻辑电路的基本方法及NAX的使用-VHDL hardware description language and digital logic circuit design

FPGA上的一个半加器实例程序，通过测试，可以直接运行在fpga开发板上。(One and a half adder example on FPGA program, through the test, can be run directly on the FPGA development board)

用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.-algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company"s paid Multiplier ip core.