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VHDLquartusmodelsim
内容有VHDL语法总结及相应的实例应用,每个程序我都亲自试过,特别适合初学VHDL的同学们。常用的程序有 设计一个M序列发生器,M序列为“11110101”、 设计一个彩灯控制器,彩灯共有16个,每次顺序点亮相邻的四个彩灯,如此循环执行,循环的方向可以控制。设计一个跑马灯控制器。一共有8个彩灯,编号为LED0~LED7,点亮方式为:先从左往右顺序点亮,然后从右往左,如此循环往复等等。这些都是我在考试前熬夜总结的,很有用。如果配合开发板用的话,那就更好了
( VHDL syntax summary content and the appropriate application instance, every program I have personally tried, especially for students of beginner VHDL. Common program has designed a sequence generator M, the M series is 11110101 , a lantern controller design, a total of 16 lights, each sequence of four adjacent lights lit, so the cycle execution cycle direction can be controlled. Marquee design a controller. A total of eight lights, numbered LED0 ~ LED7, the lighting way: first left to right order of light, and then right to left, so the cycle and so on. These are all I stay up all night before the exam summary, very useful. When combined with the development board, then so much the better
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- 2016-05-15 14:51:51下载
- 积分:1
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A4_Uart_Top
说明: 串口! 这是一个使用的通信程序 , 非常好用。(serial port Serial port! This is a communication program used, very useful.)
- 2020-06-17 14:00:01下载
- 积分:1
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Synthesis of Majority/Minority Logic Networks
;随着CMOS技术达到其物理极限,新技术
- 2023-05-15 00:50:02下载
- 积分:1
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hdb3a
快速实现HDB3码与普通码二进制码的转换,方便学习与了解HDB3码的转换(Quickly achieve HDB3 code and common code binary code conversion, facilitate learning and understanding HDB3 code conversion)
- 2020-11-09 15:09:48下载
- 积分:1
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FIFO
fifo异步串口收发程序 FPGA程序(fifo asynchronous serial transceiver)
- 2014-05-07 21:28:49下载
- 积分:1
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一个UART协议验证
一个 ;通用异步接收器/发送器UART,简称 ; ;/ˈ居ːɑːRT /,是 ;计算机硬件 ;设备之间的数据并行转换 ; ;和 ;serialfo
- 2022-04-10 03:32:48下载
- 积分:1
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PWM
通过一个计数器来实现输出信号的占空比要求,可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)
- 2020-06-16 13:20:02下载
- 积分:1
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list_ch06_02_debounce
Eliminate the program of key bounce
- 2012-12-23 00:22:42下载
- 积分:1
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lvds_ctr_top
说明: 用verilog编写的LVDS接口驱动程序,采用IOSERDES技术实现,经过Spartan6 FPGA调试验证,有完整的工程。(The LVDS interface driver written in verilog is implemented using IOSERDES technology. After Spartan6 FPGA debugging and verification, there is a complete project.)
- 2020-03-16 10:29:10下载
- 积分:1
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基于UVM的 CRC电路验证程序
基于UVM的CRC电路验证程序,包含基本的CRC电路模块,testbench,给出了UVM的实现
- 2022-02-13 03:15:19下载
- 积分:1