atm码

用Verilog实现自动售货机功能，代码较初级。易懂，内含test文件。(Automatic vending machines function with Verilog code than the primary. Understandable, containing test files.)

说明：  一个vivado和matalab混合编程的信号发生器，注意要把vivado里面的核文件路径改一下(A signal generator with mixed programming of vivado and matalab, pay attention to changing the path of the core file in vivado)

QFSK的调制与解调，用C写的主程序，汇编写的调制与解调的子程序(QFSK the modulation and demodulation, with the main program in C, compile writing, the modulation and demodulation of the Subprogram)

改自特权同学verilog语言写sdram测试程序；支持256M内存(verilog sdram )

应用背景创建一个新的Quartus II工程将用于在Altera DE2的电路实现—系列板。这个项目应该包含一个包含适当的输入和输出的顶级模块在Altera板端口。实例化你的处理器在顶层模块。使用开关sw15−0驱动该处理器使用开关SW17驱动运行输入DIN输入端口。同时，利用按键KEY0在时钟resetn和KEY1。将处理器总线导线ledr15−0和连接完成信号以LEDR关键技术该项目可用于8位处理器验证。你可以设计你自己的8位处理器，它通过验证代码。该代码用于verilog平台

本文研究的IIC总线控制器具有如下特征 1.兼容飞利浦I2C标准，以主机模式与外围设备进行数据通信，对IIC从机模型进行读/读，读/写，写/写，写/读[18]。 2.多主操作 3.软件可编程时钟频率 4.时钟拉伸和等待状态生成 5.软件可编程确认位 6.时钟同步设计 7.仲裁中断丢失，自动转移取消 8.开始/停止/重复启动检测/确认生成 9.总线忙检测(The IIC bus controller studied in this paper has the following characteristics. 1. Compatible with Philips I2C standard, data communication between host mode and peripheral devices, read/read, read/write, write/write, write/read for IIC slave model [18]. 2. Multiple Main Operations 3. Software programmable clock frequency 4. Clock stretching and waiting state generation 5. Software Programmable Confirmation Bit 6. Clock Synchronization Design 7. Loss of arbitration interruption and cancellation of automatic transfer 8. Start/Stop/Repeat Start Detection/Verification Generation 9. Bus busy detection)

在Quartus II 上编程的基于FPGA的LED显示实验(Programming in the Quartus II LED display experiment based on FPGA )

说明：  FPGA串口实现。 发送和接受数据功能代码(FPGA serial interface. Send and receive data function code)

说明：  FPGA接收串口UART发来的指令设定温度报警值，实时采集DS18B20温度传感器并显示，带报警功能(FPGA receives the instruction from UART, sets the temperature alarm value, collects and displays DS18B20 temperature sensor in real time, with alarm function)

基于IP核RAM的同步fifo设计，工程使用Xilinx的开发软件ISE(RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE)