登录
首页 » VHDL » 这是我自己编写的三分频,也就是奇数分频,占空比为1:1,当然如果需要其它奇数分频,只要将程序里面的N和counter修改即可...

这是我自己编写的三分频,也就是奇数分频,占空比为1:1,当然如果需要其它奇数分频,只要将程序里面的N和counter修改即可...

于 2022-10-27 发布 文件大小:645.60 kB
0 167
下载积分: 2 下载次数: 1

代码说明:

这是我自己编写的三分频,也就是奇数分频,占空比为1:1,当然如果需要其它奇数分频,只要将程序里面的N和counter修改即可-This was my third prepared by the frequency, which is odd hours, frequency and duty ratio of 1:1. Of course, if the needs of other odd hours, frequency, as long as the proceedings inside the N and counter can be amended

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 16位并行相关器的VHDL程序
    16位并行相关器的VHDL程序-16 parallel with the VHDL-related procedures
    2022-02-09 15:11:47下载
    积分:1
  • SPWM
    基于FPGA的正弦脉宽调制波vhdl代码,同时输出正弦波与SPWM(Sine pulse width modulation wave VHDL code based on FPGA, at the same time with SPWM output sine wave)
    2021-04-06 23:39:02下载
    积分:1
  • iq_balance
    调整iq幅度不平衡的模块,可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)
    2021-04-23 17:48:47下载
    积分:1
  • ccd
    自己写的一个tcd1209d的时序驱动代码,是用verilog语言编写的,可以借鉴(Of write a tcd1209d of timing-driven code, Verilog language, can learn from)
    2021-04-08 09:39:00下载
    积分:1
  • It s a 8051 VHDL source code issued by Original.
    它是一个8051 VHDL源代码发布的原创。
    2022-06-17 06:19:21下载
    积分:1
  • Farrow
    说明:  matlab代码,利用Farrow结构设计分数延时滤波器,滤波器阶数和个数可分别进行设置,利用最大最小准则近似。(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)
    2021-03-28 22:29:11下载
    积分:1
  • codeloc1k
    说明:  实现电子密码锁的各项功能,经过编译和仿真(Electronic code lock of the function, the compiler and simulation)
    2008-11-09 21:24:14下载
    积分:1
  • fifo
    一个FIFO产生程序,主要是一个格雷码的加法器(A FIFO generation process, is primarily a gray code adder)
    2011-08-28 10:39:31下载
    积分:1
  • uart-for-fpga
    Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.
    2020-06-24 22:00:02下载
    积分:1
  • Verilog 下脉冲发生器的源代码,可用于模拟三相交流电过零点,主要用于调试一些类似SVC(无功补偿)控制器的一些算法...
    Verilog 下脉冲发生器的源代码,可用于模拟三相交流电过零点,主要用于调试一些类似SVC(无功补偿)控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) controller of a number of algorithms
    2023-06-15 23:20:03下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载