这是我自己编写的三分频，也就是奇数分频，占空比为1：1，当然如果需要其它奇数分频，只要将程序里面的N和counter修改即可...

16位并行相关器的VHDL程序-16 parallel with the VHDL-related procedures

基于FPGA的正弦脉宽调制波vhdl代码，同时输出正弦波与SPWM(Sine pulse width modulation wave VHDL code based on FPGA, at the same time with SPWM output sine wave)

调整iq幅度不平衡的模块，可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)

自己写的一个tcd1209d的时序驱动代码，是用verilog语言编写的，可以借鉴(Of write a tcd1209d of timing-driven code, Verilog language, can learn from)

它是一个8051 VHDL源代码发布的原创。

说明：  matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似。(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)

说明：  实现电子密码锁的各项功能,经过编译和仿真(Electronic code lock of the function, the compiler and simulation)

一个FIFO产生程序，主要是一个格雷码的加法器(A FIFO generation process, is primarily a gray code adder)

Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.

Verilog 下脉冲发生器的源代码，可用于模拟三相交流电过零点，主要用于调试一些类似SVC（无功补偿）控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) controller of a number of algorithms