这是我自己编写的三分频，也就是奇数分频，占空比为1：1，当然如果需要其它奇数分频，只要将程序里面的N和counter修改即可...

复旦cpu COS

FPGA神经网络设计（影印本），全英文，很有用(FPGA neural network design (photocopies), all in English, very useful)

xilinx CTC IPcore 误码率测试-xilinx CTC IPcore Bit Error Rate Test

青云开发的LCD模块LCM240128ZK3用于ALTERA的FPGA，自己写的AVALON总线IP核，供大家参考-err

ISE Design Suite Software Manuals and Help - PDF Collection,ISE 软件手册以及帮助。(ISE Design Suite Software Manuals and Help- PDF Collection, ISE software manuals as well as help.)

电子琴程序设计与仿真的vhdl实现的源代码-Electronic organ program design implementation and simulation of vhdl source code

msttr是用vhdl语言开发的一个交通灯程序-msttr VHDL language is a development of the traffic lights procedures

这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off.

BCH3.c,提供m<21以下的所有码长的BCH编解码模块。以供大家参考。谢谢(BCH encoder&decoder GF(2^m) m<21)

fifo程序代码，程序编写，测试仿真图形，方便，比较实用(fifo code, programming, testing, simulation graphics, convenient and more practical)