FPGA控制PWM的程序

从零开始的Xilinx DDR3 控制程序编写教程，利用MIS IP核通过自编逻辑实现对DDR3的读写，强烈推荐(This is a zero to start Xilinx DDR3 control program written tutorial, the use of MIS IP kernel through the self compiled logic to achieve DDR3 reading and writing, strongly recommended.)

这是乘数 2 位数 4 位，第 4 部分实验室 6-行使的 Altera DE2 工具包的解决方案 乘数包括 2 位数 4 位输入，我使用的开关SW11−8 代表人数A 和交换机SW3−0 来表示 B.的十六进制值 A 和 B 都要上 7 段显示显示 HEX6 和 HEX4， 分别。结果 P = × B 是要显示在HEX1和HEX0上。 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

FPGA用于实现crc16编码的verlog源程序，用到的请下载。(FPGA is used to achieve the the crc16 the encoding of verlog source code used to download.)

vmm log 验证平台，采用vmm搭建 (vmm log verification platform, built by vmm)

说明：  OFDM信号的发送与接收 ，需要自取。时域图，模糊图，削峰。(Sending and receiving of OFDM signal)

基于FPGA器件的DDS设计实现中的一个核心部分就是波形存储表的设计。首先采用LPM_ROM和 VHDL选择语句这两种方法进行波形存储表的设计和比较分析 然后考虑到硬件资源的有限性及DDS的精度要 求,对这两种方法的程序进行了优化 最后对这两种方法设计的程序进行仿真和硬件调试。结果表明:采用这两种 方法都能有效地实现DDS中波形存储表的设计。 (DDS-based FPGA devices designed to achieve one of the core of the waveform is stored in table design. First of all, choose to adopt LPM_ROM and VHDL statements of these two methods for the design waveform storage tables and comparative analysis and then, taking into account the limited hardware resources and the accuracy of DDS, the two methods to optimize the process the last of these two methods of process design simulation and hardware debugging. The results showed that: the use of these two methods are all effective ways to achieve the DDS waveform stored in the table design.)

The IEEE 30-bus modified test system has 6 synchronous machines with IEEE type-1 exciters, 4 of which are synchronous compensators, 36 buses, 37 transmission lines, 10 transformers and 21 constant impedance loads. The total load demand is 283.4 MW and 126.2 MVAr.

《Verilog HDL 程序设计教程》9("Verilog HDL Design Guide" 9)

时钟司程序测试所选定的值 （32 位）。填空 Altera QuartusII Verilog。

特权同学主讲的FPGA设计的时序约束专题（STA部分）(Speaker privileged classmates timing constraints for FPGA design topics (STA section))