fpga Verilong 实现以太网

说明：  我测试过的！Verilog HDL实现RS编码。(I' ve tested it! RS coding Verilog HDL implementation.)

VERILOG HDL pid算法 带仿真验证(pid by verilog HDL)

加减可控制的十到十六进制计数器。完全准确，可以放心使用的(Add and subtract controllable ten to hexadecimal counter. Entirely accurate, can be at ease of use)

PLL 锁相环verilog程序 可以直接使用(The PLL can be used directly good use)

说明：  基于FPGA设计的一段测试VGA接口的VHDL小程序\功能为在显示器上间隔显示横条、竖条以及棋盘格等彩条信号，希望对初学FPGA驱动VGA接口的电子爱好者有用(FPGA-based design of a VGA interface VHDL test applet \ functions for the intervals shown in the display bar, vertical bars and checkerboard patterns and other signals of color, hope for beginners FPGA VGA interface driver useful for electronic enthusiasts)

说明：  关于quartus与modelsim 仿真(about quartus and modelsim simulator)

一种基于FPGA 实现DDDR SDRAM的控制器 (DDDR SDRAM controller based on FPGA)

Verilog HDL 语言编写的（15，7,2）BCH编码和译码功能(Verilog HDL language (15,7,2) BCH encoding and decoding functions)

伽罗华域的乘法器的设计，使用有限域设计乘法器(Galois field multiplier design, the use of finite field multiplier design)

verylog语言编程，为异步flipflop的程序。具有数据传输功能，数据位数可以用户设定(verylog language programming for asynchronous Flipflop procedures. With a data transmission function, data can be user set the median)