fpga Verilong 实现以太网

FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)

2、处理器的指令系统采用了MIPS  CPU的常用指令，处理器结构参考MIPS的体系结构进行设计。总线宽度为32位。 3、完成的MIPS指令集： R型：SLLV，SRAV，ADDU，SUBU，AND，OR，XOR，NOR，SLT，JR J型：J I型：BLTZ，BGTZ，BEQ，LW，SW，ADDIU，SLTI，ANDI，ORI，XORI。

FIFO is a First-In-First-Out memory queue with control logic that manages  the read and write operations, generates status flags, and provides optional  handshake signals for interfacing with the user logic. It is often used to  control the flow of data between source and destination. FIFO can be  classified as synchronous or asynchronous depending on whether same clock  or different (asynchronous) clocks control the read and write operations. In  this project the objective is to design, verify and synthesize a synchronous  FIFO using binary coded read and write pointers to address the memory  array. FFIO full and empty flags are generated and passed on to source and  destination logics, respectively, to pre-empt any overflow or underflow of  data. In this way data integrity between source and destination is maintained.  The RTL description for the FIFO is

说明：  该代码，只用了硬件描述语言Verilog在完成对SD卡控制器的编写，经济实用(The code, only the hardware description language Verilog in the completion of the SD card controller to prepare, economical and practical)

DDR3控制器源码，针对XilinxFPGA的DDR3控制器的源码，已经验证通过。(DDR3 Controller，complete DDR3 controll，have pass verificaion.)

说明：  华为FPGA设计全套资料，学习FPGA的朋友可以下载看看。(Huawei FPGA design a full set of materials, friends learning FPGA can download and see.)

rs255编码解码器，verilog描述，FPGA实现(RS255 223 ENCODER)

说明：  串口操作源代码，本代码采用veilog hdl语言编写，并经过本人多次验证。(source code, the code used veilog HDL language, and after I repeatedly verified.)

真是基于matlab的QPSK，格雷码，瑞利衰减信道，加性高斯白噪声仿真(Really based on matlab QPSK, Gray code, Rayleigh fading channel additive white Gaussian noise simulation)

Turbo编码的FPGA实现，采用了（7，5）RSC编码和循环移位交织，帧长度128bit(The FPGA implementation of Turbo coding adopts (7, 5) RSC coding and cyclic shift interleaving, and the frame length is 128bit.)