verilog实现CPU处理系统

2FSK的matlab仿真，叠加了高斯白噪声(2FSK matlab simulation, superimposed on a Gaussian white noise)

VHDL Code For Full Adder By Data Flow Modelling

基于FPGA的运动控制系统设计，包含位置、速度控制等(motion control)

FPGA锁相环实验： 顶层文件加底层IP文件构成 top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)

51数字钟带各种扩展年，月，日等并且可预置。用汇编语言写的(51 digital clock with extended assembly language)

说明：  小波变换的开源代码（Verilog HDL）包括有测试文件，本人看过，挺好。(code of dwt)

verilog 实现的FFT 流水线操作，速度能达到200M(verilog pipelining the FFT implementation, the speed can reach 200M)

本示例为基于FPGA红色飓风一代IDS-EP1C6/12开发板的USB传输，实现了pc端接收来自FPGA开发板的数据，并显示条纹，具体使用说明见解压后的说明文档。(This example is based on red hurricane generation FPGA development board' s USB transfer IDS-EP1C6/12 realized pc client receives the data from the FPGA development board and display stripes, detailed instructions, see the documentation after decompression.)

jesd204b接收部分程序和带仿真历程(Jesd204b receiving part program and simulation process)

actel公司用于1553总线的1553BRT-EBR核心代码 包括文档和代码非常有用(Actel company for the 1553 bus 1553BRT-EBR core code, including documentation and code is very useful)