verilog实现CPU处理系统

说明：  基于quartus的布斯乘法器的verilog 实现。布斯乘法算法是计算机中一种利用数的2的补码形式来计算乘法的算法。该算法由安德鲁·唐纳德·布斯于1950 年发明，当时他在伦敦大学伯克贝克学院做晶体学研究。布斯曾使用过台式计算器，由于用这种计算器来做移位计算比加法快，他发明了该算法来加快计算速度。(The verilog codes of booth multiplier based on quartus. Booth multiplication algorithm is a computer algorithm using the complement form of number 2 to calculate the multiplication. The algorithm was invented in 1950 by Andrew Donald booth, who was working on crystallography at birkbeck college, university of London. Booth used a desktop calculator, and because it was faster to do shifts than to add, he invented the algorithm to speed up the calculations.)

This is counter with T_FF.

密码锁，大学数字eda课程顺序锁的源代码，有2位或者4位的顺序锁，可以在fpga或者cpld上实现 (Password lock, digital eda course the order of the source code of the locks, the order of two or four locks, and can be implemented on the fpga or cpld)

Two-Dimensional Rank Order Filter Author: Gabor Szedo

实现米粒状态机 用verilog语言实现状态机的过程(Implement a state machine with a grain of rice verilog state machine language course)

programe reverse a string in c

使用Xilinx3S400开发的钢板检测算法中心化算法，通过测试。(a vhdl-program use Xilinx3S400)

基于用户自定义模块的实时时钟的设计；Qsys硬件设计；(Custom real-time clock module-based design Qsys hardware design )

verilog编写的GPS /BD基带逻辑代码，包含跟踪相关部分代码，有比较好的借鉴意义。

说明：  利用FPGA实现TMDS接口标准，可用于DVI以及HDMI接口的FPGA实现（含文档）(Video Connectivity Using TMDS I/O in Spartan-3A FPGAs)