fpga 按键控制数码管

Verilog投币式手机充电仪 清华大学数字电子技术基础课程EDA大作业。刚上电数码管全灭，按开始键后，数码管显示全为0。输入一定数额，数码管显示该数额的两倍对应的时间，按确认后开始倒计时。输入数额最多为20。若10秒没有按键，数码管全灭。(Verilog coin operated cell phone charger EDA major homework of digital electronic technology foundation course, Tsinghua University. Just put on the digital tube completely extinguished, press the start button, the digital tube display is 0. Enter a certain amount, the digital tube shows the amount of double the corresponding time, according to the confirmation began countdown. The maximum amount of input is 20. If there is no button in 10 seconds, the digital tube will die out.)

基于旋转编码器和LED灯组的强度调节系统设计(Design of Intensity Regulation System Based on Rotary Encoder and LED Lamp Set)

镁光SDRAM Verilog仿真模型 Company:  Micron Technology, Inc. Model:  MT48LC4M32B2 (1Meg x 16 x 4 Banks) Description:  Micron 128Mb SDRAM Verilog model

简单状态机描述的同步FIFO，包括读写计数器，空满标志位的控制。可实现顺序读写数据，包括测试文件，仿真结果正确。 filelist:fifo.v,fifo_test.v

fpga实现ＣＡＮ总线控制器源码,每个项目都有说明文件，介绍使用方法。(fpga CAN Bus Controller source, each with explanatory documents on the use of methods.)

E1成帧器和解帧器的FPGA实现源码，测试可用(E1 Framer deframer)

用Verilog语言实现了UART串行通信协议(Verilog language used to achieve a UART serial communication protocol)

说明：  本代码是控制DS1302的VHDL代码，浅显易懂，方便修改，注意看data sheet，保证时钟和各个延迟满足要求即可(This code is to control the DS1302' s VHDL code, easy to understand, easy changes, note the data sheet, ensure the clock and can meet the requirements of the various delays)

是基于FPGA的5620的数模转换芯片底层的应用程序，希望有用。(Is a digital-analog converter chip underlying the 5620 FPGA-based applications, and I hope useful.)

说明：  之前一直找不到自学编写了一个，PID案例，分享下(I have been unable to find a self-taught, compiled a PID case, share under)