反设计的VHDL例子，使用QuickLogic ECLIPS

VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source

四位加法器 数码管显示 组合电路 verilog(adder4 smg display combitional circuit verilog)

串口程序 VHDL-Serial procedures VHDL

PLL中的TDC和DCO代码,是TI公司团队的，相当经典的代码，非常不错(the code of TDC and DCO)

资源描述针对于Virtex5FPGA的DDR2读写测试的完整工程,已测试可以使用，可以根据自己的ddr2配置自行更改。。。。

针对32位MIPS微处理器中CLZ指令（对单个字高位连零进行计数）的实现电路，使用了类似于超前进位的逻辑结构。包含测试文档，以及Design Compile所用的环境和脚本。(The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The number of leading zeros is counted and the result is written to the GPR rd. If all 32 bits are cleared in the GPR rs, the result written to the GPR rd is 32. )

FPGA编程实现串口通信，源代码全。包括仿真程序。-FPGA programming serial communications, the entire source code. Including the simulation program.

华为内部资料，华为FPGA全套资料，包括华为的专利设计(Internal information Huawei Huawei FPGA complete information, including Huawei' s patented design)

这是一个用VHDL语言实现的非常实用的表决器-This is a VHDL language with the very practical voting machine

黑金动力原创nios ii教程，介绍了硬件、软件开发流程，提供了led、中断、串口、rtc、spi、iic、定时器等十多个实验的详细介绍(Alinx original nios ii tutorial, this paper introduces the hardware and software development process, and provides led, interrupt, a serial port, the RTC, spi, iic, timer and so on more than a dozen experiments in detail)