SOPC PWM IP

hdlc协议的相关程序，用verilog语言编写，供大家交流学习(hdlc protocol procedures using Verilog language for the exchange of learning)

说明：  反应力测试 利用图片的变换根据用户点击的反应时间判断(Reaction force measurement using the picture of the transformation reaction time based on user clicks judgment)

此VHDL语言程序可以控制液晶屏幕任意动画播放(The VHDL language program can control the LCD screen any animation)

使用Quartus II 9.1完成俄罗斯方块游戏，只要使用有VGA和键盘接口的FPGA开发板就行实现。操作简单，使用的是VHDL和Verilog语言(Use the Quartus II 9.1 to complete the tetris game, as long as you use a VGA and keyboard interface implementation of FPGA development board. The operation is simple, the use of VHDL and the Verilog language)

基于Montgoery 算法的RSA,FPGA verilog 实现，有测试文件(Based on Montgoery algorithm for RSA,FPGA verilog implementation，bench file)

spansion file system包括FTL功能, 支持NAND, NOR, SPI flash.(spansion file system including FTL module, support NAND, NOR, SPI flash.)

说明：  基于HSPICE实现的反相器链，并分析电路延时(Inverter chain based on HSPICE, and analyze circuit delay)

The PID controller IP core performs digital proportional–integral–derivative controller (PID controller) algorithm. The algorithm first calculates the error between a measured value (PV) and its ideal value (SP), then use the error as an argument to calculate the manipulate value(MV). The MV will adjust the process to minimize the error. It can be used to calculate duty cycle for PWM (Pulse Width Modulation).

利用systolic_arry实现矩阵的乘法/求逆等操作  矩阵为4*4矩阵   所发压缩包为ISE14.6的整个开发工程。