UART 变送器

说明：  基于FPGA，用verilog hdl语言实现串口收发实验(Based on FPGA, using Verilog HDL language to achieve serial port transceiver experiment)

资源描述一个基于verilog的VGA显示小球游戏，可在FPGA板上运行

生成bt656数据格式，针对视频adv7127芯片(Generate bt656 data format,)

Xilinx Licenses 2018

FPGA为altera的EP4CE10F17C8,AD芯片为TLC519，验证成功，可以进行小电压数模转换

SDRAM_DDR控制器verilog代码及中文说明文档。(The SDRAM_DDR controller Verilog code and documentation in chinese.)

FPGA用于实现crc16编码的verlog源程序，用到的请下载。(FPGA is used to achieve the the crc16 the encoding of verlog source code used to download.)

dds ad9910配置的verilog hdl程序，模块化设计，输入待配置的数据，字长，启动信号，即可自动产生时序，完成一次配置，模块还有done握手信号，方便用户调用时，反复多次配置。(dds ad9910 configuration verilog hdl program, modular design, the input data to be configured, word length, the start signal, the timing can be automatically generated, complete a configuration, the module has done handshake, user-friendly call, repeatedly configuration .)

基于SystemC的Uart模型-----文档(SystemC the Uart model of----- document)

连续相位调制CPM信号的viterbi编解码(MSK viterbi decode)