数字时钟Verilog

viterbi decode by verilog

对于学习FPGA的同学来说仿真是必不可少的流程 但是仿真的方法signal tap是必须掌握的(For students learning FPGA simulation is an essential process but the simulation method tap signal is a must)

设计一个8位的简易频率计，测出信号的频率，即1s内变化的次数。(An 8-bit simple frequency meter is designed to measure the frequency of the signal, i.e. the number of changes in one second.)

APB主机和从机中的Verilog实现。主机和从机的状态机设计，AHB主要用于低带宽外设。

verilog描述的基于LMS的自适应噪声消除器ANC算法。用于数字音频处理。(The verilog Description LMS-based adaptive noise canceller ANC algorithm. For digital audio processing.)

基于Verilog HDL出租车计费系统的研制(Based on Verilog HDL Taxi Accounting System)

verilog 典型电路设计包含各种常用电路的源码和详细的解释，适合新手使用(Verilog typical circuit design includes a variety of commonly used circuit source code and detailed explanations, suitable for beginners to use )

本编译码器，为码长在信息位为288码长，码率为3/4的短码LDPC编译码器，目前为最出版串行编译码，资源占比小，模块化，可扩展为半并行，缩短延时，LDPC矩阵可根据需要定制变更，测试平台文件在文件夹中的simulation中。

基于FPGA的神经网络硬件实现中的关键问题研究，适合用fpga研究神经网络的工程人员参考(FPGA-based hardware implementation of neural networks in the study of key issues for research with neural networks fpga reference works)

将BT656数据流转换成RGB图像格式的数据(Converting BT656 data stream into RGB image format)