FPGA实验，实现了蜂鸣器发出不同的音调，利用按键，很好玩的...

Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,

用VHDL语言编写的代码，以供大家学习和交流，方便大家学习！-prepared using VHDL code for all to study and exchange to facilitate learning!

掌握二-十进制(BCD码)异步计数器的工作原理和设计方法； 掌握中规模集成二-五-十进制异步计数器74LS90的功能及其应用；(Master II- Decimal (BCD code) the principle and an asynchronous counter design grasp the scale of integration in two- five- Decimal asynchronous counter 74LS90 features and applications )

使用vhdl语言在altera公司的up3板上产生vga信号，里面有详细的解析和说明，是一个很好的教程。和上一个文件razzle差不多，但是产生的效果不一样。-use of the VHDL language ALTERA company"s board up3 have vga signal containing a detailed analysis and explanation is a good guide. And on a razzle almost document, but the effects are not the same.

basic cpu design in verilog

字长可以简单调整，即可实现任意字长UART通讯(The word length can be simply adjusted to achieve any word length UART communication.)

Use full for knowing board details while making projects on FPGA and matlab simulations

this files describes how to build i2c block modules in verilog hdl and programming them on an fpga device

2004 SNUG of systemverilog

ds1302时钟驱动程序，已在quartus上验证可以是直接使用(DS1302 clock driver, which has been verified on quartus, can be used directly)