FPGA实验，实现了蜂鸣器发出不同的音调，利用按键，很好玩的...

system Verilog combinational logic

本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.-I prepared for the sentinel division, the development of software for the ISE6.2 Xilinx, PAR through simulation.

verilog实现的“BCD/七段译码器”。-verilog implementation " BCD/Seven-Segment Decoder."

说明：  基于Xilinx Spartan6系列的fpga的VGA实现(Based on Xilinx Spartan6 series fpga VGA implementation)

文章详细讲述了sdr_sdram控制器的使用和编程思想(sdr_sdram)

一位全加器的VHDL源码与TEST BENCH.XILINX下通过(A full adder and the VHDL source code through TEST BENCH.XILINX)

verilog实现的“状态机实现AD574数模转换”-verilog to achieve a " state machine to achieve AD574 digital-analog conversion"

说明：  杜晓斌和陈兴文-FPGA和单片机串行通信接口的实现一文提出了FPGA与单片机实现数据串行通信的解决方案。在通信过程中完全遵守RS232 协议，给出了发送模块的vhdl源代码。 (杜晓斌and陈兴文-FPGA single-chip serial communication interface and the realization of a text proposed by the FPGA and MCU serial data communications solutions. In the communication process in full compliance with the RS232 protocol is given to send the VHDL source code modules.)

利用FPGA实现硬件的VHLD语言的Manchester code。(Hardware implementation using FPGA VHLD language Manchester code.)

ethernet mac vhdl verilog basic