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jtag
verilog jtag源码及原理,还有debug模块。边界扫描等(verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.)
- 2021-04-27 14:18:44下载
- 积分:1
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cla - Copy
说明: ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER
- 2019-03-19 01:35:37下载
- 积分:1
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M25P80 serial memory for applications Verilog program
针对串行存储器M25P80应用的verilog程序-M25P80 serial memory for applications Verilog program
- 2022-03-12 06:10:14下载
- 积分:1
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DE2_115_CAMERA
d5m的DE2驱动Verilog HDL (d5m driven on DE2 by Verilog HDL )
- 2020-07-09 20:38:55下载
- 积分:1
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ALOHA
this program is a simulation for Aloha
- 2012-11-13 11:38:10下载
- 积分:1
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EDA设计实验,用VHDL编写的数字时钟代码,能显示分,秒,小时。根据所设置的频率不同,能够调整时间快慢。...
EDA设计实验,用VHDL编写的数字时钟代码,能显示分,秒,小时。根据所设置的频率不同,能够调整时间快慢。-EDA design of experiments, prepared by VHDL code digital clock showing the hours, seconds, hours. According to the frequency of different settings, time to adjust speed.
- 2022-10-28 17:25:03下载
- 积分:1
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example16-dac7512-sina-wave-ok
VHDL 基于cpld EPM570的DA转换代码(VHDL CPLD EPM570 the DA conversion code based on)
- 2014-12-08 14:02:34下载
- 积分:1
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Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。...
Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。-Variable Reduction Testbench is a MATLAB module that allows the application of several methods for variable reduction based on correlation analysis
- 2022-03-21 18:04:20下载
- 积分:1
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VHDL 算术逻辑单元ALU_复旦
我是复旦的研究生。这是用VHDL写的ALU,仿真通过,压缩包里包括了每个源代码,而且都有相应的testbench,你直接加入你的工程当中就可以进行验证。设计时。我使用Modelsim环境来编写的。
- 2023-06-11 02:05:03下载
- 积分:1
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Endat2_1_freq
用verilog实现endat2_1驱动,并用signalTap捕捉信号。(Using verilog achieve endat2_1 drive and use signalTap capture signal.)
- 2021-04-26 15:08:45下载
- 积分:1