Verilog HDL 程序设计实例

说明：  这个事VHDL基础知识，内面主要内容是编码器的插V过程，值得下载学习！(it is really useful for those who never touch it!)

用ALTERA的FPGA实现UDP通信源代码(FPGA UDP)

数字下变频（DDC）在如今基于软件无线电的架构中对系统的整体性能决定性的影响，代码为基于Matlab的4通道DDC程序，程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值(Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code for the 4-channel DDC Matlab-based program, the program can be adjusted according to filter parameters such as the use of performance assessment FPGA DDC DDC has achieved great reference value)

讲述软解调很不错的一片文档，主要阐述的是8PSK的软解调FPGA实现，但对8PSK的软解调原理阐述很清楚，没有多余的东西，但需要注意其中各个调制符号点得顺序。(About soft demodulation of a document is very good, mainly on the soft 8PSK demodulation FPGA, but soft 8PSK demodulation principle describes very clearly, no extra stuff, but need to pay attention to the point where each modulation symbol was in order.)

basic verilog code on siso, piso, sipo

此vhdl程序实现了在FPGA上构建UART通信串口。分为两部分，UART的发送端transfer和接收端receiver。需要外部根据需求提供波特率时钟。(This program implements the building vhdl UART serial interface on the FPGA. Divided into two parts, UART transfer sender and receiver receiver. Required to provide the baud clock external demand.)

说明：  用 AD9910实现的DDS 线性调频信号,调试已通过 可以使用(DDS LFM signal realized by ad9910 has passed debugging and can be used)

音频编码（ADPCM位） ；

FPGA实现增量式光栅尺正交脉冲解码，基于Verilog(FPGA realization of incremental grating ruler orthogonal pulse decoding, based on Verilog)

此功能需要写在你的模块结束或在您的测试台，显示你的定点实数。