FIR filter basic verilog code for implementation

动态获取CPU使用率源码 可以加到压力测试里(Dynamic access to CPU use the source code )

用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)

BulkIn是FPGA向CY7C68013发送数据 BulkOut是FPGA从CY7C68013接收数据,可以用LED显示 -BulkIn is the FPGA to the CY7C68013 is BulkOut send data CY7C68013 receive data from the FPGA, you can use LED display

Convolutional neural network code for fpga

详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE(Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE)

说明：  Verilog数字系统设计教程(第二版) 夏宇闻(Verilog Digital System Design Course (2nd Edition) Xia Yuwen)

ＡＤ转换代码，主要练习，没有具体的功能可以实现的，因为只是一部分(AD conversion code, practice, no specific function can be realized, because only part)

我是VHDL的初学者，这是我自己编译的简单的几个VHDL码，功能有3-8解码器及其testbench,16位寄存器及其testbench和交通灯。 希望能和其他初学者一起讨论学习，并得到高手的指点-I VHDL beginners, this is my own translation of a few simple VHDL code. 3-8 function decoder and testbench, 16 Register and testbench and traffic lights. Hopes to be able to discuss other beginners learning, and with the guidance of the master

基于AT89C51的密码锁（掉电可记忆密码）的程序(Based on AT89C51 lock (down to remembering passwords) program)

ALTERA官方板子DE2官方代码，芯片是EP2C35F672C6N(ALTERA official board DE2 official code, the chip is EP2C35F672C6N)