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square_syn
说明: 平方环载波同步法FPGA实现的verilog代码(square loop carrier wave syn)
- 2021-03-04 23:59:32下载
- 积分:1
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基于FPGA的乐曲发生器电路设计 附含源代码(quartersii环境下运行)...
基于FPGA的乐曲发生器电路设计 附含源代码(quartersii环境下运行)-FPGA-based circuit design of the music generator containing the source code is attached (quartersii environment to run)
- 2022-02-16 04:27:54下载
- 积分:1
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20190717 - Copy
this describes building spi block on verilog hdl and programming them on an fpga device
- 2020-06-21 21:40:02下载
- 积分:1
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A useful practical VHDL Tutorial, it is suitable for beginners to learn, introdu...
一个很有用的vhdl实用教程,很适合初学者学习,介绍了vhdl的一些基本概念,还有一些经典的实例。-A useful practical VHDL Tutorial, it is suitable for beginners to learn, introduced some basic concepts of VHDL, there are some classic examples.
- 2023-02-25 04:05:07下载
- 积分:1
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Zedboard
上传的是基于Xilinx的新出的开发板Zedboard的一个简单的知道文档,希望对有关同学有所帮助。(Uploaded a simple know the document based on Xilinx' s new development board Zedboard the hope that some of the students to help.)
- 2012-12-17 15:48:11下载
- 积分:1
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Datasheets
关于ALTERA DE2板上的文档资料,包括应用实例,用户文档和板上常用器件的技术文档(datasheets of ALTERA DE2)
- 2010-03-10 10:14:08下载
- 积分:1
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VHDL_programs
VHDL programmes for basic digital circuits. begineers can learn easily
- 2013-09-28 13:46:58下载
- 积分:1
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VHDL与源代码包
VHDL与源代码包-and VHDL source code
- 2022-04-27 02:45:55下载
- 积分:1
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digital scan conversion modules, the digital content can scan, which can also be...
数码扫描显示转换模块,可以对数码内容进行扫描,同时可进行转换-digital scan conversion modules, the digital content can scan, which can also be converted
- 2022-06-14 06:36:33下载
- 积分:1
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uart_byte_rx
说明: libero soc工程,实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)
- 2020-06-21 09:20:01下载
- 积分:1