cpld/fpga Integral comb filter (CIC) design

用Verilog语言编写的对m序列进行汉明码编译码的程序。具体实现为产生m序列后对其进行(7,4)汉明码编码并加错，然后将其纠错译码并输出，详细过程见仿真。(Written by Verilog m sequence of procedures for coding and decoding Hamming codes. Concrete realization of m sequence to produce its (7,4) hamming code and a mistake, and then error correction decoding and output, see the detailed process simulation.)

dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-dds dspbuilder under the VHDL source code and test incentives document matl ab model, the simulation under through modelsim

shift example for verilog

说明：  利用fpga实现gmsk的调制并仿真，全部代码(Fpga implements gmsk)

CAN VHDL Code. Behavioral implementation of CAN bus interface.

建立了单相的PWM整流器电路闭环控制的仿真模型。版本R2007(The simulation model of the closed-loop control of single-phase PWM rectifier circuit. Version R2007)

ByteBlasterII 下载线的制作-Download ByteBlasterII production line

说明：  spi通用串行总线，4线控制，可读写操作(SPI universal serial bus, 4-wire control, readable and writable operation)

一个用vhdl硬件描述语言实现的一个比较简单的除法器-an divider using vhdl

VHDL数字系统设计和工程实践5，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice 4, including the principles, truth table and schematic, as well as VHDL source code.