cpld/fpga Integral comb filter (CIC) design

一个用VerilogHDL语言编写的模6的二进制计数器-a Verilog HDL language used in the preparation of the six-binary counter

离散余弦变换及反离散余弦变换的HDL代码及测试文件。包括VHDL及Verilog版本。可用途JPEG及MEPG压缩算法。-Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.

说明：  stm32f103 usart 控制led灯(STM32F103 USART control LED)

该程序实现的N位全减器，首先实现一位的减法器，之后实现N位全减器。-Program of the N-bit-wide reduction, the first realization of a subtraction for, after all N-reduction devices.

全部通过，是我的精心设计，完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.

国外经典verilog代码，很适合初学者，其中的有些概念对老手也可以考虑下-Foreign classic Verilog code, it is suitable for beginners, of which some of the concept of a veteran may also want to consider under the

FPGA数字AGC(帮同学做的毕业设计)-FPGA digital AGC (help students to do the graduation project)

使用matlab实现cdma 系统的rake接收机，比较最大比合并，等增益合并和选择性合并接收算法的性能(脢 鹿 脫脙matlab脢渭脧脰cdma 脧渭脥 鲁 渭脛rake 陆 脫脢脮 禄煤 拢 卢 卤 脠 陆 脧 脳 卯)

11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated

这一计划表明它是如何在如此逻辑门是门NAND，什么它NAND它是结合两个闸门之一，并没有。