cpld/fpga Integral comb filter (CIC) design

test bench for alu 6 functions

本文介绍了使用verilog语言进行硬件设计的一些基本技巧-This paper describes the use of Verilog hardware design language, the basic skills

MBD-FPGA数字滤波器设计基本流程,基于DSP builder(MBD-FPGA basic process of digital filter design)

利用Verilog语言编写的，在vivado环境下带进位标志的全加器的工程文件与Testbench(Engineering files and Testbench of the full adder with the carry mark in vivado environment written by Verilog language)

PCI总线仲裁参考设计，Quicklogic提供的verilog代码-PCI bus arbitration reference design, pioneered the Verilog code

DE2-115开发板TV摄像头成像程序，源码亲测可用，可加入边缘算法成像，实时显示轮廓，速度流畅(The DE2-115 development board TV camera imaging procedures, the pro-test in the source can be added to the edge algorithms imaging, real-time display contours, fast-paced)

ofdm_cp_insertion add/remove CP

基于fpga的fskpsk信号产生器，可实现对1.2kHz和2.4kHz正弦波的采样-based on the fpga and fskpsk signal generator,can achieve sample to the 1.2kHz and 2.4kHz sin wave

基于DS1302芯片的VERILOG 语言数字钟。可实现年月日时分秒显示。(DS1302 chip-based language VERILOG digital clock. Date can be achieved when every minute display.)

16位有符号和无符号乘法器FPGA源代码(16-bit signed and unsigned multiplier FPGA source code)