cpld/fpga Integral comb filter (CIC) design

说明：  一种用verilog语言实现的霍夫曼压缩编码算法(Huffman compression implemented by Verilog)

二进制转十进制BCD码 Verilog语言 quartusII(Binary to decimal BCD code Verilog language quartusII)

安富利SP605开发板ISE12.4版本的XBD文件，里面包括了开发板所有的接口，包括硬件和软件设计(Avnet SP605 development board ISE12.4 version XBD file, which includes the development board all interfaces, including hardware and software design)

This is a divider, which is depicted as well. It is a programming language Vhdl.

同步FIFO功能，verilog语言描述，通过了modelsim 6.0 仿真，Quartue综合-Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated

spi通用串行总线，4线控制，可读写操作(SPI universal serial bus, 4-wire control, readable and writable operation)

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)

A Dec example written in VHDL.

VHDL语言100例详解，北京理工大学ASIC研究生出版，这里是51~94个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC publication, here is the 51 ~ 94 examples

Two-Dimensional Rank Order Filter Author: Gabor Szedo