cordic算法verilog实现代码

this is the vhdl code for the arithmetic logic unit.enjoy!

主要是基于FPGA(EP2C8Q208I8)下的SRAM驱动，SRAM型号为IS61LV25616，程序语言为Verilog,开发环境为quartusII 7.0,为一工程，可直接下载到FPGA中，含电路图(Mainly based on FPGA (EP2C8Q208I8) driving under the SRAM, SRAM model IS61LV25616, programming language for Verilog, a development environment for quartusII 7.0, for a project, can be downloaded directly to the FPGA, including circuit diagrams)

shift example for verilog

节约资源型 8位*8位 运算VHDL代码，采用串行运算，8 个时钟周期完成一次运算。QUARTUS下已验证(resource conservation-8* 8 Operational VHDL code, using serial computation. 8 clock cycles to complete an operation. QUARTUS has been under test)

完成RS（5，3）编码程序，运用Verilog语言。(Complete the RS (5,3) coding process, the use of Verilog language.)

该工程用verilog编写，已通过串口调试助手调试通过，接收模块采采用8倍波特率采样数据，有较好的滤波功能，在PC上完成自发自收功能。 (The project is written in verilog debugging through serial debugging assistant, adopted 8 times the baud rate sampling data receiver module, better filtering done on the PC spontaneous self-closing function.)

Verilog 编写的串口通信模块 带测试代码(Verilog prepared by the serial communication module with a test code)

基于FPGA的16QAM调制程序,基于verilog开发环境(16QAM modulation program based on FPGA-based development environment verilog)

Demo program for use UART STM8S

说明：  uart implementation and documentation, this describes the basic steps in building your own uart module on verilog and programming them on an fpga device