智能交通控制系统

数字频率计，测量范围0-1GHZ,测周测频自动转换，精度极高，花了很长时间，不过还是有一点点小问题，有待改进.(Digital frequency meter, range 0-1GHZ, automatic conversion measured weekly frequency measurement, high precision, took a long time, but still a little small problems to be improved.)

利用Verilog语言编写的，在vivado环境下带进位标志的全加器的工程文件与Testbench(Engineering files and Testbench of the full adder with the carry mark in vivado environment written by Verilog language)

说明：  this code works with spi and uart interfaces.

说明：  图像边缘检测，图像中值滤波和MATLAB处理(Digital Image processing based on FPGA)

saber的仿真模型，是一个电源的，经过调试已经成功(The simulation model of the saber, is a power, after commissioning has been successfully)

A Full adder using half adder unit in vhdl

verilog code for 8 bit alu

原理图输入法制作的32位加法器。。。。。。。。(adder32)

（1）MTI （2）用FFT实现MTD （3）用FIR滤波器实现MTD ((1) MTI (2) using FFT realization MTD (3) with the FIR filter implementation MTD)

51数字钟带各种扩展年，月，日等并且可预置。用汇编语言写的(51 digital clock with extended assembly language)