用硬件描述语言编程实现减法器,实现两个操作数的减法

pngenerator的vhdl代码。我们可以在cdma的fpga实现中使用它；

利用cordic实现直角坐标与极坐标的转换，用vhdl实现-use cordic achieve very Cartesian coordinates with the conversion, with vhdl achieve

many matlab code with Fftseq ,uniform to gauss AM DSB FM modulation

这是我本人自己开发的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合与与仿真，并在FPGA上测试过。能进行修改支持其他大小图像的sobeel边缘检测，同时还能实现其它的图像模块化处理算法，例如高斯滤波，平滑等。 (This is my own development vhd file, can be used for 256* 256 size image sobel edge detection under QuartusII or MaxplisII synthesis and with simulation, and tested on FPGA. Can be modified to support other sobeel size image edge detection, while still achieving other image the modular processing algorithms, such as Gaussian filtering and smoothing.)

802.11a Transmitter implementation Using Verilog

设计一个十进制计数器，具有显示位置随计数时钟在八个数码管中左右滚动的功能。(Design of a decimal counter, a display position with the count clock in at around eight digital scrolling function.)

VerilogHDL.自动增益控制模块中产生控制电压的部分-VerilogHDL. Automatic Gain Control Module have some control voltage

小波分析wave analysiswave analysiswave analysis(wave analysiswave analysis)

说明：  PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller. Tools (gcc, binutils, etc..) can be obtained via the RISC-V Website. The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in /opt/riscv32i[m][c]. See the build instructions below for details.

本程序实现不同频率时钟的产生及其相互转化-this program different clock frequencies to the formation and transformation