运动员反应时间测量电路

说明：  基于FPGA的VGA驱动代码VHDL 在显示屏显示一个汉字(FPGA-based VHDL code of the VGA driver that a character in the display)

状态机的典型饮用，可供学习模仿之用，四个状态，简单易学(State machine of the typical drinking, can be used to learn to imitate, four state, easy to learn)

说明：  将BT656数据流转换成RGB图像格式的数据(Converting BT656 data stream into RGB image format)

encoder using else if statement

tdma参数化模块。可以自动生成2的n次的tdma哥时隙，用户可根据需要自己配置参数(tdma see the number of model lumps. 2 n basis following manner tdma chance possible 以自 dynamic generation, for root needed self-placement see number)

说明：  实现FPGA多字节的稳定串口通信，改编自特权同学的FPGA代码(Realize the stable serial communication of multi-byte FPGA and adapt the FPGA code from Quan via Quartus by Verilog)

basic verilog code on siso, piso, sipo

this project is about FIR FIlter By VHdl codes in the ISE.

CAN VHDL Code. Behavioral implementation of CAN bus interface.

verilog source code for SD card SLAVE DEVICE IP-Core