交通灯控制器

Two-Dimensional Rank Order Filter Author: Gabor Szedo

我重视基本的向上和向下计数器。这不是基本up_down counter.this编码方法不同有关。

说明：  I2C完整代码，可综合，可仿真，已经过验证(I2C code can been syn and simulation ,veritify)

基于DE2-115开发板设计的一个数字钟，能进行正常的小时、分、秒计时功能，并分别由开发板上面的数码管显示秒（60s）、分（60min）、小时（24hours）的时间。并具有手动调整时间的功能(DE2-115 board design based on a digital clock, and enables the normal hours, minutes, seconds chronograph function, and were above the development board digital display seconds (60s), points (60min), hours (24hours) time . And has a function to manually adjust the time)

异步串行传输的verilog hdl 功能文件以及测试文件(The verilog hdl source and the testbench of asynchronous serial transmission )

包括Cyclone II EP2C20 原理图.CycloneII开发板原理图fpga.EP1C3T144 FPGA develop board manual.EP1C6Q240C6开发板原理图.EP2C8开发板原理图.EPM1270F256C5 MAX_II_board_schematics.SF-EP1V2+FPGA开发板原理图.XC3S400红色飓风开发板原理图.红色飓风II代开发板原理图2.(Including the Cyclone II EP2C20 schematic . CycloneII development board schematics fpga.EP1C3T144FPGA develop board manual.EP1C6Q240C6 development board schematic . EP2C8development board schematics . EPM1270F256C5MAX_II_board_schematics.SF-EP1V2+FPGA development board schematic . XC3S400red hurricane development board schematics. Red hurricane II development board schematic diagram2)

EP2C35A实验箱基于NIOSII的串行AD_DA编程(EP2C35A experimental box based NIOSII the serial AD_DA programming)

qpsk的fpga实现，包含调制和解调部分，使用verilog语言(FPGA implementation of QPSK)

本程序是锁相环的仿真程序，具有接收端载波同步的功能。注释详尽，程序规范。发端的调制方式有单载波调制，BPSK调制，QPSK调制可供选择。程序中有星座图，锁相环的频差、相差图，以及解调后的基带波形。(This program is a phase-locked loop simulation program, the with carrier synchronization receiving end function. Notes detailed program specifications. The originator of the modulation scheme to choose a single carrier modulation, BPSK modulation, QPSK modulation. Program constellation diagram, the PLL frequency difference, a difference of FIG, and the demodulated baseband waveform.)

通过FPGA驱动DM9000的程序源代码，可以实现UDP协议传输，长时间测试速率不掉，可以参考