-
xilinx_lib.tar
用于modelsim仿真的xilinxfpga平台IP库,以ise 13.x为基础制作,在modelsim10下验证通过。(xilinx IP core library for modelsim simulate, based on ise 13.x, verified in modelsim10.)
- 2017-10-27 12:23:53下载
- 积分:1
-
segment
This source is used to control 7 segments on FPGA boad
- 2014-11-10 13:33:13下载
- 积分:1
-
按键控制VGA显示
FPGA verilog VGA显示 用按键控制VGA显示不同的图像
- 2022-01-31 10:27:01下载
- 积分:1
-
freq_100M
用于检测100MHZ频率,带51单片机软核,控制外部液晶显示器以及按键等(Used to detect 100MHZ frequency, with 51 SCM soft core, control of external LCD monitors and buttons, etc.)
- 2017-07-28 09:57:56下载
- 积分:1
-
my_or
verilog 或门程序 初学者必备。。。。。。。。。。。。(verilog )
- 2009-05-26 16:07:42下载
- 积分:1
-
SystemOfTaxiFeeBasedOnVerilogHDL
摘 要:以上海地区的出租车计费器为例,利用Verilog HDL语言设计了出租车计费器,使其具有时间
显示、计费以及模拟出租车启动、停止、复位等功能,并设置了动态扫描电路显示车费和对应时间,显示
了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优
化,下载到EPF1OK10TC144—3芯片中,可应用于实际的出租车收费系统。
关键词:Verilog HDL;电子自动化设计;硬件描述语言;MAX+PLUSⅡ(Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ)
- 2007-09-11 10:52:52下载
- 积分:1
-
defog
图像去雾算法FPGA实现,使用xilinx Vivado开发环境(Image dehazing algorithm FPGA implementation using xilinx Vivado development environment)
- 2021-02-18 15:49:45下载
- 积分:1
-
how-to-use-modelsim
逐步演示试用modelsim建立仿真的过程,初学者应该看看(Step by step demonstration of the trial to establish modelsim simulation process, beginners should look at the)
- 2009-04-17 09:13:35下载
- 积分:1
-
ALU con operaciones de suma · · 雷斯塔
》 后简单 que 准许 observar la programación de diversas funcionalidades en una ALU en verilog 的 usando instrucciones de 》 后 muy 明了。
- 2022-02-11 23:41:42下载
- 积分:1
-
SPI
design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)
- 2010-08-17 19:16:12下载
- 积分:1