基于 FPGA 的红跟踪

这是用Verilog写的RS485通信程序，可以使用，希望大家能够互相交流，(This is a Verilog writing RS485 communication program, can be used, I hope we can communicate with each other,)

完成交通灯的所有功能，已经通过验证。希望大家多多指教。(Completion of all the features of traffic lights, have been authenticated. Hope the exhibitions.)

本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)

Xilinx user constraints file for the cpld xc9536 or xc9536xl or xc9572 or xc9572xl

使用verilog语言设计的512位RSA加密处理器代码，保护测试模块。 设计的代码简单易懂，适合学习FPGA的新手查阅。 代码已经经过FPGA板上测试通过，保证可以运行。

利用matlab，对偏振控制器进行仿真，最终在邦加球上进行显示(Using matlab, simulation of the polarization controller eventually be displayed on the Poincare Sphere)

verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏(verilog description of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted, within the simulation images png screenshots)

VGA 640x480 driver in verilog

说明：  利用FPGA实现对外设按键的控制，例如用户库用按键控制跑马灯的效果(FPGA is used to realize the control of external keys, such as the effect of user database using keys to control the running horse lamp)

3g-sdi驱动器，用于全高清视频FPGA解决方案(3g-sdi driver)