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my_uart
一个简单的UART串口程序,能实现数据的发送与接收,但没有奇偶校验等验证数据传输是否正确。(A simple UART serial program, can send and receive data, but there is no parity and other validation data is correct.)
- 2011-08-17 20:48:11下载
- 积分:1
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Character_LCD
This Book description about LCD in Board DE2
- 2012-07-06 11:28:58下载
- 积分:1
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bmistree_Project_Proposal
project proposal of verilog language that is gud for beginners
- 2011-04-25 00:31:03下载
- 积分:1
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AD9516VERILOG
通过VERILOG编写的AD9516时钟芯片SPI配置代码(CONGIGURE THE ad9516)
- 2021-03-15 12:09:23下载
- 积分:1
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xapp1161
多相滤波系统的设计与实现,有MATLAB仿真程序,有sysgen的系统仿真,还有VHDL代码,其中还有FIR的系数参数等等(Polyphase filter system, the design and implementation includes a MATLAB simulation program, sysgen system simulation, and VHDL code, including FIR coefficient parameters, and so on
)
- 2021-02-15 17:29:47下载
- 积分:1
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出租车模块设计加nios2设计cup程序代码
出租车模块设计加nios2设计cup程序代码...
出租车模块设计加nios2设计cup程序代码
出租车模块设计加nios2设计cup程序代码-Taxi modular design design cup plus nios2 code taxi modular design design cup plus nios2 code
- 2022-03-06 17:30:37下载
- 积分:1
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cf_ad9649_ebz_edk_14_4_2013_03_19.tar
说明: ad9649的fpga驱动程序,FMC接口,基于Xilinx KC705(AD9649 Evaluation Board, FMC Interposer & Xilinx KC705 Reference Design)
- 2020-06-28 14:00:02下载
- 积分:1
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FPGA应用举例,非常适合初学者,高手莫下
FPGA应用举例,非常适合初学者,高手莫下-FPGA application, for example, very suitable for beginners, experts, under Mo
- 2022-10-06 03:30:03下载
- 积分:1
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DDSVHDLCODE
本人收集的多个VHDL语言编写的正弦波发生器以及SPWM程序。(I collected multiple VHDL language of sine wave generator SPWM program.)
- 2021-04-06 22:39:02下载
- 积分:1
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rs232_receiver
RS232接收程序 无奇偶校验位 并行输出8位数据与data_ready数据准备好信号(RS232 receive procedures without parity 8-bit parallel output data and data ready signal data_ready)
- 2009-07-06 19:56:52下载
- 积分:1