verilog实现pwm波

VHDL 源码模块，可以实现最经典原PWM，可以用于电源，电机的控制()

包含一个ALU，实现斐波那契数列的计算。1.接受两个6位二进制输入。2.通过手动输入的时钟驱动每个周期进行一次计算。3.结果输出到led灯（使用NEXYS4开发板）(Including an ALU to realize the calculation of Fibonacci sequence. 1. Accept two 6-bit binary inputs. 2. Each cycle is driven by a clock input manually. 3. Output to LED lamp (using NEXYS4 development board))

通过用vivado完成一个流水灯项目手把手教你如何使用vivado，内容十分详细。(Using vivado to complete a running light project, you can learn how to use vivado by hand. The content is very detailed.)

其一个数码时钟和闹钟，写在 verilog 的spartan 6，用户可以设置的帮助下电钮，伸直谴责的按钮实施，在正常操作中时钟滴答，然后控件来处理 Alaram 系统中，当 alaram 的时间匹配时钟原始时间的运行然后四个指示灯开始闪烁在该套件

利用FPGA控制VGA显示器显示字符汉字的程序，里面有注释。(VGA display with FPGA control procedures Kanji characters, there are comments.)

FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)

运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。(Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.)

说明：  100个vhdl例子，对初学者很有用，可以用MAX+PLUS 2来编译仿真的(100 vhdl example, useful for beginners, you can use the MAX+ PLUS 2 to compile the simulation)

本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)

使用VHDL编写数字蜂鸣器音乐，整个项目文件，可直接使用 (Use VHDL to write 1602led driver, the entire project file, and can be used directly.)