Description Sramoc (K, M) said the figures used in 0,1,2 ..., K

Parallel to Serial converter Module

FPGA，VHDL语言 ：分频1S 8位流水灯，适用于所有FPGA芯片，VHDL源程序！！(FPGA, VHDL language: divide-1S 8 light water, and apply to all FPGA chip, VHDL source code! !)

针对Altera的DE2/ DE1交互板的音频核心的音频编解码器（编码器/解码器），并提供了音频输入和输出的接口。(The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and output.)

本代码绝对真实可靠，VHDL语言写的FPGA呼吸灯。大家可以参考学习，对于VHDL入门还是很有帮助的。库 ieee ； 使用 ieee.std_logic_1164.all ； 使用 ieee.std_logic_arith.all ； 使用 ieee.std_logic_unsigned.all ；已通过编译，已实现呼吸灯功能。 

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adding custom ip EDK

papers based on distributed arithmetic.

基于ISP的交通灯设计，实现了各路状态转换、警察控制、行人请求功能。(ISP traffic light design, to achieve the brightest state transitions, police control, pedestrian request feature.)

基于网口的收发数据及解析数据内容的verilog代码实现(Based on the Internet port to send and receive data and parse the contents of the data verilog code)

ANALYSIS OF D-FLIPFLOPS