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基于VHDL的RS232通讯程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用...
基于VHDL的RS232通讯程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL based on the RS232 communication procedures, including complete source code, locking pin, as well as download files documents can be directly downloaded using
- 2023-07-14 19:45:03下载
- 积分:1
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ANALYSIS-OF-FULL-ADDER
DESCRIPTION OF FULL ADDER
- 2013-11-12 13:32:19下载
- 积分:1
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Priority encoder in VHDL.
Priority encoder in VHDL.
- 2022-01-30 18:57:28下载
- 积分:1
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sdram_module3
能够实现16位的SDRAM的读写,没有仿真文件,只有SDRAM读写的源代码,用Verilog编写(can complete read or write sdram, only include Verilog code and no simulation files)
- 2013-11-25 12:43:11下载
- 积分:1
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用VHDL语言在CPLD上实现串行通信
用VHDL语言在CPLD上实现串行通信-using VHDL on the CPLD Serial Communication
- 2022-02-15 15:58:59下载
- 积分:1
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HDMI_FPGA
该源码可基于FPGA设置多分辨率的HDMI显示,且其包含了完整的时序和端口、地址映射,可以很方便的将其移植(The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted)
- 2020-12-17 11:09:12下载
- 积分:1
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串口程序,基于VHDL 的,很好的程序
快下吧
串口程序,基于VHDL 的,很好的程序
快下吧-Serial procedures, based on VHDL, and a very good program, are you fast
- 2022-02-04 10:08:53下载
- 积分:1
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pipelined_fft_256
verilog编写的并行256点fft代码(Verilog prepared parallel 256 points fft code)
- 2017-06-28 21:56:53下载
- 积分:1
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wide_cbf
宽带波束形成,设计FIR滤波器系数。带宽为500Hz--700Hz,采样率为3000Hz,对白噪声序列进行滤波,即得到有限带宽的宽带时域信号(Broadband beamforming design FIR filter coefficients. Bandwidth of 500Hz- 700Hz, sampling rate of 3000Hz, filtered white noise sequence, ie limited bandwidth broadband time domain signal)
- 2013-03-19 09:40:45下载
- 积分:1
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Camera-Interface-Overview
主要讲述了数码相机MIPI接口协议说明,工作模式及信号传输原理等(Camera Interface Overview)
- 2014-01-20 22:19:32下载
- 积分:1