CPLD drives with digital control, of from 0000 to 9999, digital control is a dyn...

booth algotihm verilog design and test

verilog lcd2864 适合初学者(verilog lcd2864 )

八阶巴特沃兹iir数字滤波器，四个二阶节，verilog代码实现，多路分时复用(batterworth，iir，8order，four second order section)

goertzel stuff. contains matlab files and different explanations of how it is used for DTMF decoding.

说明：  数电实验FPGA verilog代码，包括秒表、全加器、半加器等。(FPGA Verilog code for digital experiment)

--author: Suntion Tang --date: 2008-6-7 -- two warning --modify: By Suntion Tang at 2008-6-14 --description: 顶层文件，由于此系统简单， -- 且底层文件不多，故放弃原理图描述，采用VHDL语言描述-author: Suntion Tang date: 2008-6-7 two warning modify: By Suntion Tang at 2008-6-14 description: the top-level documents, as a result of this system is simple, and not more than the bottom of a document, they give up the schematic description of the use of VHDL language description

un controller pi par le langage VHDL xilinx ise design 13.2

基于FPGA的 温度传感器 DS18B20接口设计-FPGA DS18B20

在matlab中8psk的调制和解调仿真程序(the modulation and demodulation of 8psk)

vhdl code for decoder and detemines the basic mechanism of gates of decoder