VGA256显示verilog程序

verilog实现千兆以太网udp传输,具有发送和接收功能。同时有CRC校核代码。学习FPGA的很好的参考资料，值得大家下载。

用Verilog编写ad_9866的相应程序，在FPGA上实现相应功能(The corresponding program of ad_9866 is written with Verilog, and the corresponding functions are realized on the FPGA.)

AD9910实现脉冲内线性调频信号，仅供参考(AD9910 to achieve linear FM pulse signal, for reference only)

dac714的控制程序，包括spi数据通信，转换控制(dac714 control procedures, including the spi data communications, switching control)

一个精确时钟的v-log程序，只用一个全局时钟，增加了精确度(An accurate clock in the v-log program, only one global clock, increased accuracy)

采用verilog语言基于查找表描述8b10b编码源代码(Using Verilog language to describe 8B10B encoding source code based on look-up table)

The Date prototype object is itself a Date object (its [[Class]] is "Date") whose value is NaN.

i2c master ip for altera nios, add in qsys

说明：  常系数有限域乘法器，verilog DHL源码(Constant coefficient finite field multiplier, verilog DHL source)

Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。 模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。 (Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)