VGA256显示verilog程序

说明：  简易信号发生器，可以实现简单的信号实现，任意波编辑，通过FPGA的verilog语言实现功能，自测可以正常使用。(Simple signal generator, can realize simple signal realization, arbitrary wave editing, through FPGA Verilog language function, self-test can be used normally.)

说明：  led学习控制l44444444444444(led verilog led ccccccc)

lbus总线：一般是两个FPGA之间的相连接总线。或者其余器件与FPGA之间的数据总线。一般的时候会设计到双向数据总线。如何完成读写的控制？这里介绍一种简易稳定的处理方法。利用IOBUF完成双向总线。

资源描述该程序是在同步FIFO的基础上实现了异步串口通信发送机的功能，首先通过数据产生模块产生数据缓存到FIFO中，然后UATR的tx模块通过检测FIFO中的数据，并将数据发送出去。

vhdl code for carry lookahead addder

verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器，分别记录在时钟上升沿时A,B,C,D的输入情况，比如某上升沿输入A，相应时刻A对应的移位寄存器输入1，其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样，密码锁不仅可以识别字符数量，还可以判断出字符的输入次序。(verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the clock rising edge A, B, C, D of inputs, such as a rising edge of input A, the corresponding moments A 1 corresponding to the input shift register, the other three shift bit register inputs are 0. another four parallel 10-bit registers record the password. This lock can not only identify the number of characters, you can also determine the character of the input sequence.)

能实现输入0.5 1 5块钱的累加，然后对应购买的商品价格进行比较，显示找的钱数或错误灯(MY English is very good)

说明：  寄存器设计文件，寄存器输入输出以及读写控制，寄存器的配置(Register design and read-write control)

8051 1Khz sine wave generator. make use of DAC0808 and timer 0 interrupt. Also single led is blinked continuously.

简单的单周期CPU设计，实现的指令有：算术运算指令、逻辑运算指令、移位指令、比较指令、存储器读/写指令、分支指令、跳转指令、停机指令。(Simple single-cycle CPU design,The instructions implemented are as follows:Arithmetic operation instruction, logical operation instruction, shift instruction, comparison instruction, memory read/write instruction, branch instruction, jump instruction, stop instruction.)