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ads8361_avl
Interface for ADS8361 TI ADC
IP Core for ALTERA NIOS2
- 2013-04-04 16:12:13下载
- 积分:1
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one_2017_v2
说明: 一个编码解码系统,其中包含一个信号发生器(用查找表方式实现)、一个m序列生成器(用来编码和解码用)、一个FiFo队列用来做缓存以及用串口方式进行收发读取数据。(An encoding and decoding system, which includes a signal generator (implemented by look-up table), an m-sequence generator (used for encoding and decoding), a FIFO queue for caching, and a serial port for receiving, transmitting and reading data.)
- 2021-03-15 18:24:40下载
- 积分:1
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comp
The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
- 2012-06-05 23:16:25下载
- 积分:1
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Fractional_Time_Delay
Used for Time shifting discrete signals, it can do both integral and fractional sampling period delay. Original.
- 2020-12-16 22:29:12下载
- 积分:1
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YCbCr2RGB
RGB 与YCbCr 颜色空间可以相互转化(RGB and YCbCr color space can be transformed into each other)
- 2016-05-01 11:11:43下载
- 积分:1
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AD_R
AD7685芯片采集程序,可以自行设置采样率,经检验可用。(The AD7685 chip collection procedures, available.)
- 2020-12-20 14:19:08下载
- 积分:1
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fft_ex1
基于verilog的FFT设计,使用vivado作为开发平台(Verilog based on the FFT design, the use of vivado as a development platform)
- 2021-02-24 23:39:39下载
- 积分:1
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XadcMicroblaze-master
用zynq实现片内的数模转换,基于最新的zynq平台(zynq xadc on FPGA arm)
- 2020-06-21 12:00:02下载
- 积分:1
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AMI1
本代码是用VERILOG语言描述的AMI码的解码的程序,经过调试是正确的。代码简单易懂。(This code is described in VERILOG language AMI code decoding process, after debugging is correct. Code is easy to understand.)
- 2021-04-22 14:48:48下载
- 积分:1
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flashZ
FPGA控制m25p16flash芯片读写控制spi协议
可实现擦除写入读出功能(SPI protocol for read and write control of m25p16 flash chip controlled by FPGA
Erase Write-Read Function)
- 2018-12-19 16:10:59下载
- 积分:1