FPGA中常用的上升沿检测和下降沿检测代码以及检测是否有边沿，使用的verilog hdl语言

说明：  基于fpga的spi通信测试 可与stm32进行spi通信测试(SPI communication test based on FPGA can test SPI communication with stm32)

基于FPGA的fsk调制程序，包括载波的生成，nco的设置(FPGA-based fsk modulation procedures, including carrier generation, nco settings)

使用Verilog语言对128点 基8FFT的实现(Implementation of 128-point basis 8FFT)

说明：  本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)

time to digital convertor

altera公司飓风四代芯片，LCD屏幕彩条显示，有效实现行、场扫描。练习FPGA驱动VGA或LCD显示的入门程序(Altera hurricane four generation chip, LCD screen color display, the effective realization of line and field scanning.Practice FPGA to drive VGA or LCD display)

9针的rs232与fpga之间的串口通信源程序(Rs232 9 pin serial communication with the source between fpga)

这是xilix项目。它是纹波进位加法器的通用代码，其测试平台也是它们的核心。它有最小的延迟。已检查。它工作正常。

如何用VHDL语言对时钟进行分频以达到计数目的(how to achive counting by VHDL Language)

非常需要的可以下载看看,适合初学者学习,好的算法和程序(Very need to download to see, suitable for beginners to learn, good algorithm and program.)