FPGA中常用的上升沿检测和下降沿检测代码以及检测是否有边沿，使用的verilog hdl语言

it is used to compile codec

this is code verilog

无线通信的MATLAB和FPGA实现，书籍，经典无线通信，代码可以实现(Wireless communication MATLAB and FPGA implementation, books, classic wireless communications, code can be achieved)

Crossroad traffic lights with visualization in tcl/tk and verilog code

4 bit ROM for Quartus

关于USB开发的verilog开发程序，非常的全面，学习FPGA开发时用得着。(About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.)

利用VHDL语言描述出一个双脉冲，可任意设置两脉冲长和中间时间间隔。(A double pulse is described in VHDL language, and the two pulse length and the intermediate time interval can be arbitrarily set.)

Token Bucket Filter queue.

基于VHDL的RS232通讯程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用(VHDL based on the RS232 communication procedures, including complete source code, locking pin, as well as download files documents can be directly downloaded using)

FPU (Floating Point Unit) is very useful in the moden ASIC and SOC designs. This module has been verified by FPGA and EDA env. But if you want to use it in a real project, please verify it with some formal method.