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无线应用的Viterbi译码器的实现
摘要:
- 2022-07-04 06:23:17下载
- 积分:1
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VHDL_example_100
本书通过100个实例,详细介绍便件描述语言vHDL的各种语法现象及其在专用集成电路(AHc)设计蝴还中的使用方法。(the book through one hundred examples, it detailed description language vHDL pieces of the phenomenon and its various grammatical in ASIC (AHc) were also designed butterfly The usage.)
- 2007-03-25 09:57:05下载
- 积分:1
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用FPGA实现GPS数据解析,Verilog测试通过
用FPGA实现GPS数据解析,基于Verilog实现,并通过串口发送时间信息
- 2022-03-02 02:41:56下载
- 积分:1
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Huffman-Decoder-master
用verilog编写的huffman解码程序(huffman decoder verilog)
- 2017-12-06 15:31:44下载
- 积分:1
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Nexys-4-DDR-XADC
Nexys-4-DDR-XADC 开发板demo(Nexys-4-DDR-XADC e.v. Board demo)
- 2018-12-07 15:33:22下载
- 积分:1
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CORDIC16
16次迭代的CORDIC算法,精度很高,可应用于计算反正切值(16 iterations of the CORDIC algorithm, high accuracy, can be applied to calculate arctangent)
- 2010-06-01 15:23:27下载
- 积分:1
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AHB 转移到 APB 源和建业读/写 verilog 代码
转换AHB外围转移到APB转移16槽孔APB桥提供高速AHB之间的界面域和低功率的APB域。大桥出现在AHB奴隶,而在APB,它是主人。读取和写入的AHB接送转换成相应的APB传输。由于APB不流水线,等待状态转移过程中加入,并从建业的时候在AHB需要等待APB协议。在AHB到APB桥包括一个状态机,它被用来控制产生的APB和AHB输出信号,以及地址解码逻辑,用于生成所述APB外设选择线。在系统中使用的所有寄存器被从的上升沿时钟系统时钟HCLK,并使用异步复位HRESETn
- 2022-04-10 17:05:22下载
- 积分:1
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verilog fifo 代码
FIFO is a First-In-First-Out memory queue with control logic that manages
the read and write operations, generates status flags, and provides optional
handshake signals for interfacing with the user logic. It is often used to
control the flow of data between source and destination. FIFO can be
classified as synchronous or asynchronous depending on whether same clock
or different (asynchronous) clocks control the read and write operations. In
this project the objective is to design, verify and synthesize a synchronous
FIFO using binary coded read and write pointers to address the memory
array. FFIO full and empty flags are generated and passed on to source and
destination logics, respectively, to pre-empt any overflow or underflow of
data. In this way data integrity between source and destination is maintained.
The RTL description for the FIFO is
- 2022-05-22 08:44:13下载
- 积分:1
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非还原分频器
Verilog 代码固定的点非还原分压器用于执行司的两个 8 位数字。它适用于无符号数字。
- 2022-02-02 09:31:28下载
- 积分:1
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实验12
说明: 数字逻辑实验课第十二次作业,基于Verilog的Clock时钟(Clock based on Verilog)
- 2021-03-11 15:03:46下载
- 积分:1