fifo的IP核的调用和仿真

基于verilog的出租车付费系统 带验证模块

采用Verilog语言，实现db8小波分解(Realizing wavelet decomposition)

Routine for I2C in VHDL

应用背景Project: A Wishbone Controlled Real--time Clock Core Purpose: Implement a real time clock, including alarm, count--down timer, stopwatch, variable time frequency, and more.关键技术基于FPGA的用verilog编写的时钟模块，具有时间计数，闹铃，以及计数器功能！具有很好的学习和使用价值。基于FPGA的用verilog编写的时钟模块，具有时间计数，闹铃，以及计数器功能！具有很好的学习和使用价值。

AD9910实现脉冲内线性调频信号，仅供参考(AD9910 to achieve linear FM pulse signal, for reference only)

说明：  该资料是用vhdl编写的按键消抖程序，按键消抖在使用按键的数字电路中非常重要，如果不对按键信号进行处理，有可能会出现大量错误的按键信号。文件key_xd.vhd是按键消抖程序，文件key_xd.vwf是仿真波形文件。该程序已经通过仿真测试，并且在电路板上调试通过，效果理想。(The information is written in the key consumer vhdl shaking procedures, key consumer shaking in digital circuits using the buttons is very important, if not key signal processing, there may be a lot of the wrong button signal. File key_xd.vhd is key consumer shake procedure is the simulation waveform file key_xd.vwf file. The program has been tested by simulation and debugging in circuit board by, the results are satisfactory.)

用以VGA显示的小程序，很实用，挺有价值的(VGA display for a small program, very practical, quite valuable)

rmii 以太网接口时序源代码，值得开发借鉴的哦(verilog hdl)

FPGA实现FFT算法的源代码及工程文件，此工程为ISE工程项目。有详细的说明，可以运行。(FPGA Implementation of FFT algorithm source code and project files, this works for the ISE project. There are detailed instructions, you can run.)

Aurora 8B/10B协议是Xilinx公司针对高速传输开发的一种可裁剪的轻量级链路层协议，通过一条或多条串行链路实现两设备间的数据传输。协议Aurora协议可以支持流和帧两种数据传输模式，以及全双工、单工等数据通信方式。(The Aurora 8B / 10B protocol is a tailor-made lightweight link layer protocol developed by Xilinx for high-speed transmission that enables data transfer between two devices over one or more serial links. Protocol Aurora protocol can support two data transfer modes, stream and frame, as well as full-duplex, simplex and other data communications.)