vivado2017+下的HDMI环路视频代码（AX7103）

3x3中值滤波器的FPGA实现现(VERILOG)可直接使用。 (3x3 median filter FPGA implementation of the present (VERILOG) can be used directly.)

使用vhdl语言设计一位全加器，在仪器上下载并实现LED灯的闪亮(A full adder design)

实现两个状态机和不同的数据传输方式，按照smbus总线的要求进行调节每位的传输，从起始位到终值位，能够较好的实现

HDB3 encoder and decoder(HDB3 decoer)

说明：  FPGA 点亮数码管的灯，本例程支持6位数码管，因为我的FPGA开发板是这样子的(The lamp of digital tube illuminated by FPGA)

设计处理最小化路由器端口五口三个端口，这样我们可以节省功耗和面积。

The SPFD5408A, a 262144-color System-on-Chip (SoC) driver LSI designed for small and medium sizes of TFT LCD display, is capable of supporting up to 240xRGBx320 in resolution which can be achieved by the designated RAM for graphic data. The 720-channel source driver has true 6-bit resolution, which (The SPFD5408A, a 262144-color System-on-Chip (SoC) driver LSI designed for small and medium sizes of TFT LCD display, is capable of supporting up to 240xRGBx320 in resolution which can be achieved by the designated RAM for graphic data. The )

基于 quartus 2 的 lte 信道估计verilog hdl代码 只有功能仿真 时序仿真自己加sdc文件并且调整testbench的clk才能做出来(Estimated Verilog HDL code based Quartus lte channel only functional simulation timing simulation plus sdc file and adjust the testbench clk to do it)

基于VHDL的SDH专用芯片的TOP-DOWN设计， 内有全套源码以及图片，内容详尽，绝对真实可靠！(VHDL based on the SDH ASIC Design TOP-DOWN, which has a full set of source code, as well as pictures, and detailed, reliable and absolutely true!)

采用Verilog语法编写的UDP协议网络  能够实现UDP包的发送和接收 采用Verilog语法编写的UDP协议网络  能够实现UDP包的发送和接收 采用Verilog语法编写的UDP协议网络  能够实现UDP包的发送和接收