这是我用vhdl语言，在fpga内部做了一个双口ram的程序。我的邮箱：wleechina@163.com...

介绍了基于Altera 公司的CPLD 芯片FL EX10 K,以及利用VHDL 语言实现多位二进 制码转换成8421BCD 码的原理、设计思路和软件实现。-Introduction based on Altera

说明：  Multiplexer 4 to 1 on Modelsim

Simple relay trigger

GE PCI5565 PMC5565 PCIE5565反射内存网数据中断接收程序 接收中断 反射内存网 VMIC5565反射内存卡 实时仿真技术 PCI5565PIORC-110000(GE PCI5565 PMC5565 PCIE5565 reflective memory network data interrupt transmission program VMIC5565 reflective memory card real-time simulation technology)

vhdl写的ds18b20程序，相互交流-vhdl written ds18b20 procedures, mutual exchange

IP 核的接口（The Avalon® Streaming (Avalon-ST) interface）的使用说明，和程序(IP core interface (The Avalon Streaming (Avalon-ST) interface) instructions for use, and procedures)

verilog 双模块算术平均值计算模块，子模块在时钟上升沿技术，高层模块根据当前计数值计算算数平均(verilog double module arithmetic mean calculation module, sub-module in the clock rising edge technology, high-level module is calculated based on arithmetic average of the current count)

主要介绍了ＦＰＧＡ设计的基本原则、基本设计思想、基本操作技巧、常用模块。-Mainly introduces the basic principles of FPGA design, basic design concepts, basic operating skills, commonly used modules.

基于状态图的光电编码器4倍频vhdl程序，输入相位差90度的两相，输出倍频和方向信号-Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, enter a 90-degree phase difference of two-phase, frequency and direction of the output signal

这是一个利用verilog语言编写的信号发生器的例子，值得参考(this is a code about signal generator by VIERILOG LANGUAGE!)