upp 接口，verilog

一个关于VERILOG与VHDL混合编程，混合验证的资料(A hybrid programming on VERILOG and VHDL, mixed verification data)

在FPGA开发板上用VHDL语言实现了贪吃蛇游戏，开发软件为quartus 2.这是详细的实验报告，包括源码(Snake game with VHDL FPGA development board, software development quartus 2 This is a detailed experimental report, including the source)

Package include hardware implementation of Lz77 algorithm

基于FPGA的16QAM调制程序,基于verilog开发环境(16QAM modulation program based on FPGA-based development environment verilog)

Verilog代码随机计数器计数的随机数，根据要求，

verilogPWM波的设计，属于数字电子技术实验入门的资料

RGMII测试程序，在板子测试验证过，可以使用，初学者可以参考下

本实验实现了一个小的乒乓游戏，VGA显示,代码下载的FPGA板子上验证通过，效果很好。(The experimental realization of a small ping-pong game, VGA display, download the code verified by the FPGA board, with good results.)

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)

使用verliog设计实现LUT查找表乘法器，通过modelsim仿真验证通过(Designed and implemented using the LUT lookup table verliog multipliers, through simulation by modelsim)