altera实现的UDP协议（Verilog实现）

对于已获得的脉冲包络采样序列，需测量的脉冲特征参数主要有：脉冲幅值(PA)、脉冲到达时间(TOA)和脉冲宽度(PW)。实际测量中，脉冲波形的形状是各种各样的，但其主要的参数有脉冲幅度、脉冲宽度、脉冲周期、脉冲占空比、脉冲前沿(上升时间)、脉冲后沿(下降时间)、脉冲上冲、脉冲下冲、脉冲下垂、脉冲顶部不平度等，脉冲参数的计量主要就是对这些参数进行计量。本程序包实现基于FPGA实现脉冲宽度和重复周期的测量。(Who have access to the pulse envelope sample sequence, the pulse measurement to be the main characteristic parameters are: pulse amplitude (PA), pulse time of arrival (TOA) and pulse width (PW). The actual measurement, the pulse shape is a wide variety of shapes, but its main parameters of the pulse amplitude, pulse width, pulse period, pulse duty cycle, pulse leading edge (rise time), pulse along (down time), the red pulse, pulse undershoot, pulse droop, pulse irregularities, such as at the top, the measurement of pulse parameters is mainly the measurement of these parameters. The package FPGA-based pulse width and repetition to achieve the measurement cycle.)

一个交通灯设计,简单的实现，没有添加其他的显示管(Traffic Light System)

说明：  基于quartusII的QDPSK调制解调vhdl程序。(Modulation and demodulation based quartusII of QDPSK vhdl program.)

将串行数据转换为并行的 Verilog 代码。从 rs232 端口的 8 位串行数据转换为 8 位并行数据。

DDS VHDL include everything of dds AD9914

基于FPGA的点灯游戏，完整工程。包括鼠标控制，键盘控制，SVGA显示等(Light game based on FPGA, the whole project which includes keyboard control, SVGA and so on.)

帧激励产生器，用于VMM仿真中生成所需要帧以供测试所用(the use for test)

crc校验，非常好用，是从Xilinx的IP演化来的(crc脨 拢 脩茅 拢 卢 脟 鲁 拢 潞 脙脫脙 拢 卢 脢脟)

说明：  verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.(Verilog language to write the SPI interface, all synchronous design, low gate count. it is very easy to use embedded design programs.)

说明：  HDMI做为视频输出输入接口已经广泛使用很长时间，主要通过TMDS差分编码传输。本实验通过在HDMI屏幕上显示彩条和输入输出环通实验，来练习视频的时序和视频颜色的表示，为后面视频处理实验做个基础。(HDMI as video output input interface has been widely used for a long time, mainly through TMDS differential coding transmission. In this experiment, by displaying color bars and input/output loop experiments on HDMI screen, video timing sequence and video color representation are practiced to lay a foundation for video processing experiments later)