用vhdl描写的通用异步改进dram控制器，经过编译器综合和仿真测试，符合设计要求。...

递增方式在4位数码管上向上计数显示从0000-0001->0002……..9999….0000….0001…. -- 利用CPLD设计了一个4位十进制计数器，并用数码管显示当前计数值-Incremental approach in the four counts upward digital tube display from 0000-0001-

三八译码器，四位加法器，EDA实验，用verilog编写(EDA experiment with verilog language)

LCD图形显示代码，已调试过，可以运行成功(LCD graphics display code has been debugged, you can run successfully)

FIFO的VERILOG代码编写 可综合的Verilog FIFO存储器(The VERILOG code FIFO write comprehensive Verilog FIFO memory)

UART自适应波特率发生器，其中是以文档的形式来介绍怎样实现UART波特率发生器的实现(Adaptive UART baud rate generator, which is in the form of a document to describe how to achieve the realization of UART baud rate generator)

分数阶Unscented卡尔曼滤波器研究.pdf(Fractional Unscented Kalman filter pdf)

基于 quartus 2 的 lte 信道估计verilog hdl代码 只有功能仿真 时序仿真自己加sdc文件并且调整testbench的clk才能做出来(Estimated Verilog HDL code based Quartus lte channel only functional simulation timing simulation plus sdc file and adjust the testbench clk to do it)

用窗函数法设计一个线性相位FIR数字低通滤波器，用理想低通滤波器作为逼近滤波器，通带截止频率为0.2 ，阻带截止频率为0.4 ，阻带衰减不小于-40dB。(Window function method to design a linear phase FIR digital low-pass filter, as an ideal low-pass filter for approximation filter passband cutoff frequency of 0.2 stopband cutoff frequency of 0.4, the stop-band attenuation of less than-40dB.)

说明：  用verilog HDL编程实现的基于DAC0832的三角波信号，可借鉴编程实现DAC0832芯片控制(Programming with verilog HDL DAC0832-based triangular wave signal, we may learn programming DAC0832 chip control)

用于altera公司DE2开发板上SD_Card_Audio的实例-DE2 development company for the altera board SD_Card_Audio examples