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DDR3
spartan6 里使用DDR3IP核,有教程以及源码(spartan6 with ddr3,source and tutorial)
- 2021-01-07 08:48:52下载
- 积分:1
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Verilog写的88E1111 GMII接口驱动代码
Verilog写的88E1111 GMII接口驱动代码,仿真通过,使用的是Xilinx的三态以太网IP核。
- 2022-06-28 22:36:43下载
- 积分:1
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SR_DDS
DDS信号源设计,有正弦波,方波,三角波,AM波,FM波,还有PSK,FSK,16QAM等多种信号产生。(DDS signal source design, there are sine, square wave, triangle wave, AM wave, FM wave, as well as PSK, FSK, 16QAM and other signal generation.)
- 2016-03-20 22:04:51下载
- 积分:1
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ModelSim_
FPGA编写环境,具有仿真容易,软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)
- 2013-07-24 19:20:57下载
- 积分:1
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LDPC编译码
LDPC编译码,最新一代纠错码技术,自带校验矩阵,数据程序内带测试数据
- 2022-01-26 04:09:36下载
- 积分:1
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matlab2DPSK
蒙特卡洛仿真图
这个程序对2psk信号进行仿真
前提是把信号能量归一化了
(This programme intend to realize the simulation of 2DPSK through MonteCarlo experiment.
intends
)
- 2013-05-04 13:18:00下载
- 积分:1
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UART_TX
说明: fpga串口的接收程序基于verilog语言拿走不用谢。(The receiving program of FPGA serial port is based on Verilog language.)
- 2020-06-18 03:20:02下载
- 积分:1
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Project_Gbit
说明: pc与fpga之间通过千兆以太网交换机实现网络通信(Network communication between PC and FPGA via Gigabit Ethernet switch)
- 2020-06-17 20:40:04下载
- 积分:1
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FIR
一个1MHz的FIR低通滤波器。
① 时钟信号频率16MHz;
② 输入信号位宽8bits,符号速率16MHz;
③ 要求在Matlab软件中进行FIR滤波器浮点和定点仿真,并确定FIR滤波器抽头系数;
④ 写出测试仿真程序。(A 1MHz FIR low pass filter.
(1) The clock signal frequency is 16MHz;
(2) The input signal has a bit width of 8 bits and a symbol rate of 16 MHz;
(3) Floating-point and fixed-point simulation of FIR filter is required in Matlab software, and tap coefficients of FIR filter are determined.
(4) Write the test simulation program.)
- 2019-06-19 21:47:13下载
- 积分:1
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youmui_v20
ICA (Principal Component Analysis) algorithm and procedures, GSM is GMSK modulation signal generation, On neural network control.
- 2017-09-01 20:51:26下载
- 积分:1