五子棋verilog

一个关于跨越异步时钟边界传输数据的解决方案(The solution of transfering data across asynchronous clock boundary.)

以太网PHY层中的组成部分 8B10B编码器(Part of the Ethernet PHY layer in 8B10B encoder )

基于VHDL语言的波形发生器编程设计，能够实现常用波形的产生。(Waveform generator design based on VHDL programming, to achieve common waveform generated.)

PID控制器的verilog实现，做闭环控制器的人可以参考(PID controller verilog implementation of closed-loop controller may make reference to)

SPI接口测试程序，Xilinx参考设计，ML507硬件测试通过.(SPI interface test code，Xilinx reference design，tested on ML507 platform.)

在BASYS3上实现跑马灯的功能。第一LED交替闪烁；第二LED由左至右逐个变亮，再逐个变暗；第三LED由右至左逐个变亮，再逐个变暗；第四LED由两边逐个变亮，再从中间逐个变暗。(Realize the function of the horse light on BASYS3. The first LED flashes alternately; second LED brightens from left to right and then darkens one by one; the third LED turns from right to left, then darkens one by one, and then darkens one by one; fourth LED is brightened by both sides, and then darkening from the middle.)

由8 位加法器构成的以时序方式设计的8 位乘法器，采用逐项移位相加的方 法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。(an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.)

实现AHB转SRAM接口实现，支持猝发，零等待延迟(Implementation of AHB to SRAM Interface)

verilog code for bus controller

本控制器与博世参考模型测试